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63 lines
1.6 KiB
Verilog
63 lines
1.6 KiB
Verilog
//-----------------------------------------------------------------------------
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// The way that we connect things in low-frequency simulation mode. In this
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// case just pass everything through to the ARM, which can bit-bang this
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// (because it is so slow).
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//
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// Jonathan Westhues, April 2006
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// iZsh <izsh at fail0verflow.com>, June 2014
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//-----------------------------------------------------------------------------
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module lo_edge_detect(
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input pck0, input [7:0] pck_cnt, input pck_divclk,
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output pwr_lo, output pwr_hi,
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output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
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input [7:0] adc_d, output adc_clk,
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output ssp_frame, input ssp_dout, output ssp_clk,
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input cross_lo,
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output dbg,
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input lf_field
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);
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wire tag_modulation = ssp_dout & !lf_field;
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wire reader_modulation = !ssp_dout & lf_field & pck_divclk;
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// No logic, straight through.
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assign pwr_oe1 = 1'b0; // not used in LF mode
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assign pwr_oe2 = tag_modulation;
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assign pwr_oe3 = tag_modulation;
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assign pwr_oe4 = tag_modulation;
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assign ssp_clk = cross_lo;
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assign pwr_lo = reader_modulation;
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assign pwr_hi = 1'b0;
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assign dbg = ssp_frame;
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assign adc_clk = ~pck_divclk;
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// Toggle the output with hysteresis
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// Set to high if the ADC value is above 200
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// Set to low if the ADC value is below 64
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reg is_high;
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reg is_low;
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reg output_state;
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always @(posedge pck0)
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begin
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if((pck_cnt == 8'd7) && !pck_divclk) begin
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is_high = (adc_d >= 8'd190);
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is_low = (adc_d <= 8'd70);
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end
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end
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always @(posedge is_high or posedge is_low)
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begin
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if(is_high)
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output_state <= 1'd1;
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else if(is_low)
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output_state <= 1'd0;
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end
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assign ssp_frame = output_state;
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endmodule
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