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dbfd8b7a6d
This adds a new command "hw sethfthresh" to configure the thresholds used inside the FPGA while demodulating ISO14443A. The thresholds need to be increased on particularly noisy hardware, such as certain Chinese PM3 Easy clones.
226 lines
8.4 KiB
Verilog
226 lines
8.4 KiB
Verilog
//-----------------------------------------------------------------------------
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// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// See LICENSE.txt for the text of the license.
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//-----------------------------------------------------------------------------
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//
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// The FPGA is responsible for interfacing between the A/D, the coil drivers,
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// and the ARM. In the low-frequency modes it passes the data straight
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// through, so that the ARM gets raw A/D samples over the SSP. In the high-
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// frequency modes, the FPGA might perform some demodulation first, to
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// reduce the amount of data that we must send to the ARM.
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//-----------------------------------------------------------------------------
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module fpga_hf(
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input spck,
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output miso,
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input mosi,
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input ncs,
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input pck0,
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input ck_1356meg,
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input ck_1356megb,
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output pwr_lo,
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output pwr_hi,
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output pwr_oe1,
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output pwr_oe2,
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output pwr_oe3,
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output pwr_oe4,
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input [7:0] adc_d,
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output adc_clk,
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output adc_noe,
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output ssp_frame,
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output ssp_din,
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input ssp_dout,
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output ssp_clk,
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input cross_hi,
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input cross_lo,
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output debug
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);
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//-----------------------------------------------------------------------------
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// The SPI receiver. This sets up the configuration word, which the rest of
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// the logic looks at to determine how to connect the A/D and the coil
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// drivers (i.e., which section gets it). Also assign some symbolic names
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// to the configuration bits, for use below.
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//-----------------------------------------------------------------------------
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// Receive 16bits of data from ARM here.
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reg [15:0] shift_reg;
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always @(posedge spck) if (~ncs) shift_reg <= {shift_reg[14:0], mosi};
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reg [8:0] conf_word;
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reg trace_enable;
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// select module (outputs) based on major mode
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wire [2:0] major_mode = conf_word[8:6];
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// parameter to be passed to modules
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wire [3:0] minor_mode = conf_word[3:0];
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// configuring the HF reader
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wire [1:0] subcarrier_frequency = conf_word[5:4];
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// We switch modes between transmitting to the 13.56 MHz tag and receiving
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// from it, which means that we must make sure that we can do so without
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// glitching, or else we will glitch the transmitted carrier.
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always @(posedge ncs)
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begin
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// 4 bit command
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case (shift_reg[15:12])
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`FPGA_CMD_SET_CONFREG: conf_word <= shift_reg[8:0];
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`FPGA_CMD_TRACE_ENABLE: trace_enable <= shift_reg[0];
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endcase
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end
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//-----------------------------------------------------------------------------
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// And then we instantiate the modules corresponding to each of the FPGA's
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// major modes, and use muxes to connect the outputs of the active mode to
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// the output pins.
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//-----------------------------------------------------------------------------
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// 0 - HF reader
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hi_reader hr(
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.ck_1356meg (ck_1356megb),
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.pwr_lo (hr_pwr_lo),
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.pwr_hi (hr_pwr_hi),
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.pwr_oe1 (hr_pwr_oe1),
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.pwr_oe2 (hr_pwr_oe2),
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.pwr_oe3 (hr_pwr_oe3),
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.pwr_oe4 (hr_pwr_oe4),
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.adc_d (adc_d),
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.adc_clk (hr_adc_clk),
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.ssp_frame (hr_ssp_frame),
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.ssp_din (hr_ssp_din),
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.ssp_dout (ssp_dout),
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.ssp_clk (hr_ssp_clk),
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.debug (hr_debug),
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.subcarrier_frequency (subcarrier_frequency),
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.minor_mode (minor_mode)
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);
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// 1 - HF simulated tag
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hi_simulate hs(
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.ck_1356meg (ck_1356meg),
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.pwr_lo (hs_pwr_lo),
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.pwr_hi (hs_pwr_hi),
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.pwr_oe1 (hs_pwr_oe1),
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.pwr_oe2 (hs_pwr_oe2),
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.pwr_oe3 (hs_pwr_oe3),
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.pwr_oe4 (hs_pwr_oe4),
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.adc_d (adc_d),
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.adc_clk (hs_adc_clk),
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.ssp_frame (hs_ssp_frame),
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.ssp_din (hs_ssp_din),
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.ssp_dout (ssp_dout),
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.ssp_clk (hs_ssp_clk),
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.debug (hs_debug),
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.mod_type (minor_mode)
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);
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// 2 - HF ISO14443-A
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`define EDGE_DETECT_THRESHOLD 3
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`define EDGE_DETECT_THRESHOLDHIGH 20
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hi_iso14443a hisn(
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.ck_1356meg (ck_1356meg),
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.pwr_lo (hisn_pwr_lo),
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.pwr_hi (hisn_pwr_hi),
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.pwr_oe1 (hisn_pwr_oe1),
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.pwr_oe2 (hisn_pwr_oe2),
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.pwr_oe3 (hisn_pwr_oe3),
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.pwr_oe4 (hisn_pwr_oe4),
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.adc_d (adc_d),
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.adc_clk (hisn_adc_clk),
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.ssp_frame (hisn_ssp_frame),
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.ssp_din (hisn_ssp_din),
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.ssp_dout (ssp_dout),
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.ssp_clk (hisn_ssp_clk),
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.debug (hisn_debug),
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.mod_type (minor_mode),
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.edge_detect_threshold (`EDGE_DETECT_THRESHOLD),
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.edge_detect_threshold_high (`EDGE_DETECT_THRESHOLDHIGH)
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);
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// 3 - HF sniff
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hi_sniffer he(
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.ck_1356meg (ck_1356megb),
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.pwr_lo (he_pwr_lo),
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.pwr_hi (he_pwr_hi),
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.pwr_oe1 (he_pwr_oe1),
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.pwr_oe2 (he_pwr_oe2),
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.pwr_oe3 (he_pwr_oe3),
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.pwr_oe4 (he_pwr_oe4),
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.adc_d (adc_d),
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.adc_clk (he_adc_clk),
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.ssp_frame (he_ssp_frame),
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.ssp_din (he_ssp_din),
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.ssp_clk (he_ssp_clk)
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);
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// 4 - HF ISO18092 FeliCa
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hi_flite hfl(
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.ck_1356meg (ck_1356megb),
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.pwr_lo (hfl_pwr_lo),
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.pwr_hi (hfl_pwr_hi),
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.pwr_oe1 (hfl_pwr_oe1),
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.pwr_oe2 (hfl_pwr_oe2),
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.pwr_oe3 (hfl_pwr_oe3),
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.pwr_oe4 (hfl_pwr_oe4),
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.adc_d (adc_d),
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.adc_clk (hfl_adc_clk),
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.ssp_frame (hfl_ssp_frame),
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.ssp_din (hfl_ssp_din),
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.ssp_dout (ssp_dout),
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.ssp_clk (hfl_ssp_clk),
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.debug (hfl_debug),
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.mod_type (minor_mode)
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);
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// 5 - HF get trace
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hi_get_trace gt(
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.ck_1356megb (ck_1356megb),
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.adc_d (adc_d),
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.trace_enable (trace_enable),
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.major_mode (major_mode),
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.ssp_frame (gt_ssp_frame),
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.ssp_din (gt_ssp_din),
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.ssp_clk (gt_ssp_clk)
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);
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// Major modes:
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// x0 = HF reader
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// x1 = HF simulated tag
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// x2 = HF ISO14443-A
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// x3 = HF sniff
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// x4 = HF ISO18092 FeliCa
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// x5 = HF get trace
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// x6 = unused
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// x7 = FPGA_MAJOR_MODE_OFF
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mux8 mux_ssp_clk (.sel(major_mode), .y(ssp_clk ), .x0(hr_ssp_clk ), .x1(hs_ssp_clk ), .x2(hisn_ssp_clk ), .x3(he_ssp_clk ), .x4(hfl_ssp_clk ), .x5(gt_ssp_clk ), .x6(1'b0), .x7(1'b0) );
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mux8 mux_ssp_din (.sel(major_mode), .y(ssp_din ), .x0(hr_ssp_din ), .x1(hs_ssp_din ), .x2(hisn_ssp_din ), .x3(he_ssp_din ), .x4(hfl_ssp_din ), .x5(gt_ssp_din ), .x6(1'b0), .x7(1'b0) );
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mux8 mux_ssp_frame (.sel(major_mode), .y(ssp_frame), .x0(hr_ssp_frame ), .x1(hs_ssp_frame), .x2(hisn_ssp_frame), .x3(he_ssp_frame), .x4(hfl_ssp_frame), .x5(gt_ssp_frame), .x6(1'b0), .x7(1'b0) );
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mux8 mux_pwr_oe1 (.sel(major_mode), .y(pwr_oe1 ), .x0(hr_pwr_oe1 ), .x1(hs_pwr_oe1 ), .x2(hisn_pwr_oe1 ), .x3(he_pwr_oe1 ), .x4(hfl_pwr_oe1 ), .x5(1'b0 ), .x6(1'b0), .x7(1'b0) );
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mux8 mux_pwr_oe2 (.sel(major_mode), .y(pwr_oe2 ), .x0(hr_pwr_oe2 ), .x1(hs_pwr_oe2 ), .x2(hisn_pwr_oe2 ), .x3(he_pwr_oe2 ), .x4(hfl_pwr_oe2 ), .x5(1'b0 ), .x6(1'b0), .x7(1'b0) );
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mux8 mux_pwr_oe3 (.sel(major_mode), .y(pwr_oe3 ), .x0(hr_pwr_oe3 ), .x1(hs_pwr_oe3 ), .x2(hisn_pwr_oe3 ), .x3(he_pwr_oe3 ), .x4(hfl_pwr_oe3 ), .x5(1'b0 ), .x6(1'b0), .x7(1'b0) );
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mux8 mux_pwr_oe4 (.sel(major_mode), .y(pwr_oe4 ), .x0(hr_pwr_oe4 ), .x1(hs_pwr_oe4 ), .x2(hisn_pwr_oe4 ), .x3(he_pwr_oe4 ), .x4(hfl_pwr_oe4 ), .x5(1'b0 ), .x6(1'b0), .x7(1'b0) );
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mux8 mux_pwr_lo (.sel(major_mode), .y(pwr_lo ), .x0(hr_pwr_lo ), .x1(hs_pwr_lo ), .x2(hisn_pwr_lo ), .x3(he_pwr_lo ), .x4(hfl_pwr_lo ), .x5(1'b0 ), .x6(1'b0), .x7(1'b0) );
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mux8 mux_pwr_hi (.sel(major_mode), .y(pwr_hi ), .x0(hr_pwr_hi ), .x1(hs_pwr_hi ), .x2(hisn_pwr_hi ), .x3(he_pwr_hi ), .x4(hfl_pwr_hi ), .x5(1'b0 ), .x6(1'b0), .x7(1'b0) );
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mux8 mux_adc_clk (.sel(major_mode), .y(adc_clk ), .x0(hr_adc_clk ), .x1(hs_adc_clk ), .x2(hisn_adc_clk ), .x3(he_adc_clk ), .x4(hfl_adc_clk ), .x5(1'b0 ), .x6(1'b0), .x7(1'b0) );
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mux8 mux_dbg (.sel(major_mode), .y(debug ), .x0(hr_debug ), .x1(hs_debug ), .x2(hisn_debug ), .x3(he_debug ), .x4(hfl_debug ), .x5(1'b0 ), .x6(1'b0), .x7(1'b0) );
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// In all modes, let the ADC's outputs be enabled.
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assign adc_noe = 1'b0;
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endmodule
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