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66 lines
2.3 KiB
Verilog
66 lines
2.3 KiB
Verilog
//-----------------------------------------------------------------------------
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// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
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//
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// This code is licensed to you under the terms of the GNU GPL, version 2 or,
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// at your option, any later version. See the LICENSE.txt file for the text of
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// the license.
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//-----------------------------------------------------------------------------
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// track min and max peak values (envelope follower)
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//
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// NB: the min value (resp. max value) is updated only when the next high peak
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// (resp. low peak) is reached/detected, since you can't know it isn't a
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// local minima (resp. maxima) until then.
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// This also means the peaks are detected with an unpredictable delay.
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// This algorithm therefore can't be used directly for realtime peak detections,
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// but it can be used as a simple envelope follower.
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module min_max_tracker(input clk, input [7:0] adc_d, input [7:0] threshold,
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output [7:0] min, output [7:0] max);
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reg [7:0] min_val = 255;
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reg [7:0] max_val = 0;
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reg [7:0] cur_min_val = 255;
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reg [7:0] cur_max_val = 0;
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reg [1:0] state = 0;
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always @(posedge clk)
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begin
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case (state)
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0:
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begin
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if (cur_max_val >= ({1'b0, adc_d} + threshold))
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state <= 2;
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else if (adc_d >= ({1'b0, cur_min_val} + threshold))
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state <= 1;
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if (cur_max_val <= adc_d)
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cur_max_val <= adc_d;
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else if (adc_d <= cur_min_val)
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cur_min_val <= adc_d;
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end
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1:
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begin
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if (cur_max_val <= adc_d)
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cur_max_val <= adc_d;
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else if (({1'b0, adc_d} + threshold) <= cur_max_val) begin
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state <= 2;
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cur_min_val <= adc_d;
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max_val <= cur_max_val;
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end
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end
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2:
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begin
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if (adc_d <= cur_min_val)
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cur_min_val <= adc_d;
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else if (adc_d >= ({1'b0, cur_min_val} + threshold)) begin
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state <= 1;
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cur_max_val <= adc_d;
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min_val <= cur_min_val;
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end
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end
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endcase
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end
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assign min = min_val;
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assign max = max_val;
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endmodule
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