Code SystemVerilog (#3462) egorguslyan

* SystemVerilog Language

* SystemVerilog quotes

Source: https://github.com/Featherweight-IP/fwrisc

* Remove temporary folder

* Lengths are still incorrect

* Fixed lengths

Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
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egorguslyan 2022-08-31 07:46:27 -03:00 committed by GitHub
parent 237a513153
commit f87f5467ad
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4 changed files with 309 additions and 1 deletions

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@ -384,7 +384,8 @@
"code_vimscript",
"code_opencl",
"code_visual_basic",
"code_arduino"
"code_arduino",
"code_systemverilog"
]
},
{

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@ -215,6 +215,7 @@
,"code_opencl"
,"code_visual_basic"
,"code_arduino"
,"code_systemverilog"
,"hindi"
,"hindi_1k"
,"macedonian"

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@ -0,0 +1,229 @@
{
"name": "code_systemverilog",
"leftToRight": true,
"noLazyMode": true,
"words": [
"alias",
"always",
"always_comb",
"always_ff",
"always_latch",
"and",
"assert",
"assign",
"assume",
"automatic",
"before",
"begin",
"bind",
"bins",
"binsof",
"bit",
"break",
"buf",
"bufif0",
"bufif1",
"byte",
"case",
"casex",
"casez",
"cell",
"chandle",
"class",
"clocking",
"cmos",
"config",
"const",
"constraint",
"context",
"continue",
"cover",
"covergroup",
"coverpoint",
"cross",
"deassign",
"default",
"defparam",
"design",
"disable",
"dist",
"do",
"edge",
"else",
"end",
"endcase",
"endclass",
"endclocking",
"endconfig",
"endfunction",
"endgenerate",
"endgroup",
"endinterface",
"endmodule",
"endpackage",
"endprimitive",
"endprogram",
"endproperty",
"endspecify",
"endsequence",
"endtable",
"endtask",
"enum",
"event",
"expect",
"export",
"extends",
"extern",
"final",
"first_match",
"for",
"force",
"foreach",
"forever",
"fork",
"forkjoin",
"function",
"generate",
"genvar",
"highz0",
"highz1",
"if",
"iff",
"ifnone",
"ignore_bins",
"illegal_bins",
"import",
"incdir",
"include",
"initial",
"inout",
"input",
"inside",
"instance",
"int",
"integer",
"interface",
"intersect",
"join",
"join_any",
"join_none",
"large",
"liblist",
"library",
"local",
"localparam",
"logic",
"longint",
"macromodule",
"matches",
"medium",
"modport",
"module",
"nand",
"negedge",
"new",
"nmos",
"nor",
"noshowcancelled",
"not",
"notif0",
"notif1",
"null",
"or",
"output",
"package",
"packed",
"parameter",
"pmos",
"posedge",
"primitive",
"priority",
"program",
"property",
"protected",
"pull0",
"pull1",
"pulldown",
"pullup",
"pulsestyle_onevent",
"pulsestyle_ondetect",
"pure",
"rand",
"randc",
"randcase",
"randsequence",
"rcmos",
"real",
"realtime",
"ref",
"reg",
"release",
"repeat",
"return",
"rnmos",
"rpmos",
"rtran",
"rtranif0",
"rtranif1",
"scalared",
"sequence",
"shortint",
"shortreal",
"showcancelled",
"signed",
"small",
"solve",
"specify",
"specparam",
"static",
"string",
"strong0",
"strong1",
"struct",
"super",
"supply0",
"supply1",
"table",
"tagged",
"task",
"this",
"throughout",
"time",
"timeprecision",
"timeunit",
"tran",
"tranif0",
"tranif1",
"tri",
"tri0",
"tri1",
"triand",
"trior",
"trireg",
"type",
"typedef",
"union",
"unique",
"unsigned",
"use",
"uwire",
"var",
"vectored",
"virtual",
"void",
"wait",
"wait_order",
"wand",
"weak0",
"weak1",
"while",
"wildcard",
"wire",
"with",
"within",
"wor",
"xnor",
"xor",
"<="
]
}

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