2010-02-21 08:12:52 +08:00
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//-----------------------------------------------------------------------------
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// (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
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2016-10-06 04:58:06 +08:00
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// 2016 Iceman
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2018-07-29 18:18:08 +08:00
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// 2018 AntiCat (rwd rewritten)
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2010-02-21 08:12:52 +08:00
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//
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// This code is licensed to you under the terms of the GNU GPL, version 2 or,
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// at your option, any later version. See the LICENSE.txt file for the text of
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// the license.
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//-----------------------------------------------------------------------------
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// LEGIC RF simulation code
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//-----------------------------------------------------------------------------
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2010-02-21 06:51:00 +08:00
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#include "legicrf.h"
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2010-02-05 16:18:02 +08:00
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2018-07-29 18:18:08 +08:00
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#include "ticks.h" /* timers */
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#include "crc.h" /* legic crc-4 */
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#include "legic_prng.h" /* legic PRNG impl */
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#include "legic.h" /* legic_card_select_t struct */
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2010-02-05 16:18:02 +08:00
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2018-07-29 18:18:08 +08:00
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static uint8_t* legic_mem; /* card memory, used for read, write and sim */
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static legic_card_select_t card;/* metadata of currently selected card */
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static crc_t legic_crc;
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static int32_t input_threshold; /* values > threshold are 1 else 0 */
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2010-02-05 16:18:02 +08:00
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2018-07-29 18:18:08 +08:00
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// LEGIC RF is using the common timer functions: StartCountUS() and GetCountUS()
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#define RWD_TIME_PAUSE 20 /* 20us */
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#define RWD_TIME_1 100 /* READER_TIME_PAUSE 20us off + 80us on = 100us */
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#define RWD_TIME_0 60 /* READER_TIME_PAUSE 20us off + 40us on = 60us */
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#define TAG_FRAME_WAIT 330 /* 330us from READER frame end to TAG frame start */
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#define TAG_BIT_PERIOD 100 /* 100us */
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2016-09-12 15:19:49 +08:00
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2018-07-29 18:18:08 +08:00
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#define LEGIC_CARD_MEMSIZE 1024 /* The largest Legic Prime card is 1k */
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2016-09-12 15:19:49 +08:00
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2018-07-29 18:18:08 +08:00
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//-----------------------------------------------------------------------------
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2018-07-30 05:58:43 +08:00
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// I/O interface abstraction (FPGA -> ARM)
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2018-07-29 18:18:08 +08:00
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//-----------------------------------------------------------------------------
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2016-09-09 17:56:20 +08:00
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2018-07-29 18:18:08 +08:00
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static inline uint8_t rx_byte_from_fpga() {
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for(;;) {
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WDT_HIT();
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2009-11-05 19:13:46 +08:00
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2018-07-29 18:18:08 +08:00
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// wait for byte be become available in rx holding register
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if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
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return AT91C_BASE_SSC->SSC_RHR;
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}
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}
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}
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2016-09-02 22:25:54 +08:00
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2018-07-29 18:18:08 +08:00
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//-----------------------------------------------------------------------------
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// Demodulation
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//-----------------------------------------------------------------------------
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2016-09-11 03:43:08 +08:00
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2018-07-29 18:18:08 +08:00
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// Returns am aproximated power measurement
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//
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// The FPGA running on the xcorrelation kernel samples the subcarrier at ~3 MHz.
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// The kernel was initialy designed to receive BSPK/2-PSK. Hance, it reports an
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// I/Q pair every 18.9us (8 bits i and 8 bits q).
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//
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// The subcarrier amplitude can be calculated using Pythagoras sqrt(i^2 + q^2).
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// To reduce CPU time the amplitude is approximated by using linear functions:
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// am = MAX(ABS(i),ABS(q)) + 1/2*MIN(ABS(i),ABSq))
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//
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// Note: The SSC receiver is never synchronized the calculation my be performed
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// on a i/q pair from two subsequent correlations, but does not matter.
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static inline int32_t sample_power() {
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int32_t q = (int8_t)rx_byte_from_fpga(); q = ABS(q);
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int32_t i = (int8_t)rx_byte_from_fpga(); i = ABS(i);
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2016-09-09 17:56:20 +08:00
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2018-07-29 18:18:08 +08:00
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return MAX(i, q) + (MIN(i, q) >> 1);
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}
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2016-09-09 17:56:20 +08:00
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2018-07-29 18:18:08 +08:00
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// Returns a demedulated bit
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//
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// An aproximated power measurement is available every 18.9us. The bit time
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// is 100us. The code samples 5 times and uses samples 3 and 4.
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//
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// Note: The demodulator is drifting (18.9us * 5 = 94.5us), since the longest
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// respons is 12 bits, the demodulator will stay in sync with a margin of
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// error of 20us left. Sending the next request will resync the card.
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static inline bool rx_bit() {
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static int32_t p[5];
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for(size_t i = 0; i<5; ++i) {
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p[i] = sample_power();
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}
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if((p[2] > input_threshold) && (p[3] > input_threshold)) {
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return true;
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}
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if((p[2] < input_threshold) && (p[3] < input_threshold)) {
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return false;
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}
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Dbprintf("rx_bit failed %i vs %i (threshold %i)", p[2], p[3], input_threshold);
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return false;
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2016-09-09 17:56:20 +08:00
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}
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2018-07-29 18:18:08 +08:00
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//-----------------------------------------------------------------------------
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// Modulation
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//
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2018-07-30 05:58:43 +08:00
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// I've tried to modulate the Legic specific pause-puls using ssc and the default
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// ssc clock of 105.4 kHz (bit periode of 9.4us) - previous commit. However,
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// the timing was not precise enough. By increasing the ssc clock this could
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// be circumvented, but the adventage over bitbang would be little.
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2018-07-29 18:18:08 +08:00
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//-----------------------------------------------------------------------------
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2016-10-06 03:42:13 +08:00
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2018-07-30 05:58:43 +08:00
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static inline void tx_bit(bool bit) {
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uint32_t ts = GetCountUS();
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2016-09-02 22:25:54 +08:00
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2018-07-30 05:58:43 +08:00
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// insert pause
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LOW(GPIO_SSC_DOUT);
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while(GetCountUS() < ts + RWD_TIME_PAUSE) { };
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HIGH(GPIO_SSC_DOUT);
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2018-07-29 18:18:08 +08:00
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2018-07-30 05:58:43 +08:00
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// return to high, wait for bit periode to end
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2018-07-29 18:18:08 +08:00
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if(bit) {
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2018-07-30 05:58:43 +08:00
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while(GetCountUS() < ts + RWD_TIME_1) { };
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2018-07-29 18:18:08 +08:00
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} else {
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2018-07-30 05:58:43 +08:00
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while(GetCountUS() < ts + RWD_TIME_0) { };
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2018-07-29 18:18:08 +08:00
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}
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}
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2015-11-10 04:51:34 +08:00
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2018-07-29 18:18:08 +08:00
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//-----------------------------------------------------------------------------
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// Frame Handling
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//
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// The LEGIC RF protocol from card to reader does not include explicit frame
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// start/stop information or length information. The reader must know beforehand
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// how many bits it wants to receive.
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// Notably: a card sending a stream of 0-bits is indistinguishable from no card
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// present.
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//-----------------------------------------------------------------------------
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2015-11-10 04:51:34 +08:00
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2018-07-29 18:18:08 +08:00
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static void tx_frame(uint32_t frame, uint8_t len) {
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);
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// transmit frame, MSB first
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2018-07-30 05:58:43 +08:00
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for(uint8_t i = 0; i < len; ++i) {
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bool bit = (frame >> i) & 0x01;
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tx_bit(bit ^ legic_prng_get_bit());
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legic_prng_forward(1);
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};
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2018-07-29 18:18:08 +08:00
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2018-07-30 05:58:43 +08:00
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// add pause to mark end of the frame
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uint32_t ts = GetCountUS();
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LOW(GPIO_SSC_DOUT);
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while(GetCountUS() < ts + RWD_TIME_PAUSE) { };
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HIGH(GPIO_SSC_DOUT);
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2010-05-06 19:24:01 +08:00
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}
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2018-07-29 18:18:08 +08:00
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static uint32_t rx_frame(uint8_t len) {
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR
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| FPGA_HF_READER_RX_XCORR_848_KHZ
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| FPGA_HF_READER_RX_XCORR_QUARTER);
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2016-10-06 03:42:13 +08:00
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2018-07-29 18:18:08 +08:00
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uint32_t frame = 0;
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for(uint8_t i = 0; i < len; i++) {
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frame |= (rx_bit() ^ legic_prng_get_bit()) << i;
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legic_prng_forward(1);
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}
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2016-09-02 22:25:54 +08:00
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2018-07-29 18:18:08 +08:00
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return frame;
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2016-09-09 17:56:20 +08:00
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}
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2016-09-02 22:25:54 +08:00
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2018-07-29 18:18:08 +08:00
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//-----------------------------------------------------------------------------
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// Legic Reader
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//-----------------------------------------------------------------------------
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int init_card(uint8_t cardtype, legic_card_select_t *p_card) {
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p_card->tagtype = cardtype;
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switch(p_card->tagtype) {
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case 0x0d:
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p_card->cmdsize = 6;
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p_card->addrsize = 5;
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p_card->cardsize = 22;
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break;
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case 0x1d:
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p_card->cmdsize = 9;
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p_card->addrsize = 8;
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p_card->cardsize = 256;
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break;
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case 0x3d:
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p_card->cmdsize = 11;
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p_card->addrsize = 10;
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p_card->cardsize = 1024;
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break;
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default:
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p_card->cmdsize = 0;
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p_card->addrsize = 0;
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p_card->cardsize = 0;
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return 2;
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}
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return 0;
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2009-11-06 23:37:53 +08:00
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}
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2018-07-29 18:18:08 +08:00
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static void init_reader(bool clear_mem) {
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// configure FPGA
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FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR
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| FPGA_HF_READER_RX_XCORR_848_KHZ
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| FPGA_HF_READER_RX_XCORR_QUARTER);
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SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
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2018-07-30 05:58:43 +08:00
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// configure SSC with defaults
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2018-07-29 18:18:08 +08:00
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FpgaSetupSsc();
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2018-07-30 05:58:43 +08:00
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// re-claim GPIO_SSC_DOUT as GPIO and enable output
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AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
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AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
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HIGH(GPIO_SSC_DOUT);
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2018-07-29 18:18:08 +08:00
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// reserve a cardmem, meaning we can use the tracelog function in bigbuff easier.
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legic_mem = BigBuf_get_EM_addr();
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if(legic_mem) {
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memset(legic_mem, 0x00, LEGIC_CARD_MEMSIZE);
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}
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// start trace
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clear_trace();
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set_tracing(true);
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// init crc calculator
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crc_init(&legic_crc, 4, 0x19 >> 1, 0x05, 0);
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// start us timer
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StartCountUS();
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2009-10-12 19:47:39 +08:00
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}
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2018-07-29 18:18:08 +08:00
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// Setup reader to card connection
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//
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// The setup consists of a three way handshake:
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// - Transmit initialisation vector 7 bits
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// - Receive card type 6 bits
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// - Acknowledge frame 6 bits
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2016-09-14 22:18:04 +08:00
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static uint32_t setup_phase_reader(uint8_t iv) {
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2018-07-29 18:18:08 +08:00
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uint32_t ts = GetCountUS();
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// Switch on carrier and let the card charge for 5ms.
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// Use the time to calibrate the treshhold.
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input_threshold = 8; // heuristically determined
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do {
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int32_t sample = sample_power();
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if(sample > input_threshold) {
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input_threshold = sample;
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}
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} while(GetCountUS() < ts + 5000);
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2009-12-29 02:19:00 +08:00
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2018-07-29 18:18:08 +08:00
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// Set threshold to noise floor * 2
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input_threshold <<= 1;
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2010-02-05 16:18:02 +08:00
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2018-07-29 18:18:08 +08:00
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legic_prng_init(0);
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tx_frame(iv, 7);
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ts = GetCountUS();
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2016-09-02 22:25:54 +08:00
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2018-07-29 18:18:08 +08:00
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// configure iv
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legic_prng_init(iv);
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legic_prng_forward(2);
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2010-02-05 16:18:02 +08:00
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2018-07-29 18:18:08 +08:00
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// wait until card is expect to respond
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while(GetCountUS() < ts + TAG_FRAME_WAIT) { };
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2010-02-05 16:18:02 +08:00
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2018-07-29 18:18:08 +08:00
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// receive card type
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int32_t card_type = rx_frame(6);
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// send obsfuscated acknowledgment frame
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switch (card_type) {
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case 0x0D:
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tx_frame(0x19, 6); // MIM22 | READCMD = 0x18 | 0x01
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break;
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case 0x1D:
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case 0x3D:
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tx_frame(0x39, 6); // MIM256 | READCMD = 0x38 | 0x01
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break;
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}
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return card_type;
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2010-05-06 19:24:01 +08:00
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}
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2010-02-05 16:18:02 +08:00
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2018-07-29 18:18:08 +08:00
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static uint8_t calc_crc4(uint16_t cmd, uint8_t cmd_sz, uint8_t value) {
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crc_clear(&legic_crc);
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crc_update(&legic_crc, (value << cmd_sz) | cmd, 8 + cmd_sz);
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return crc_finish(&legic_crc);
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2010-05-06 19:24:01 +08:00
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}
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2018-07-29 18:18:08 +08:00
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static int16_t read_byte(uint16_t index, uint8_t cmd_sz) {
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uint16_t cmd = (index << 1) | LEGIC_READ;
|
2015-01-16 18:00:17 +08:00
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2018-07-29 18:18:08 +08:00
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// read one byte
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tx_frame(cmd, cmd_sz);
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uint32_t frame = rx_frame(12);
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2016-07-29 03:41:44 +08:00
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2018-07-29 18:18:08 +08:00
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// split frame into data and crc
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uint8_t byte = BYTEx(frame, 0);
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uint8_t crc = BYTEx(frame, 1);
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// check received against calculated crc
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uint8_t calc_crc = calc_crc4(cmd, cmd_sz, byte);
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if(calc_crc != crc) {
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Dbprintf("!!! crc mismatch: %x != %x !!!", calc_crc, crc);
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return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return byte;
|
2016-09-29 23:43:39 +08:00
|
|
|
}
|
2016-09-29 18:23:09 +08:00
|
|
|
|
2016-10-07 01:13:23 +08:00
|
|
|
//-----------------------------------------------------------------------------
|
2018-07-29 18:18:08 +08:00
|
|
|
// Command Line Interface
|
|
|
|
//
|
|
|
|
// Only this functions are public / called from appmain.c
|
2016-10-07 01:13:23 +08:00
|
|
|
//-----------------------------------------------------------------------------
|
2018-07-29 18:18:08 +08:00
|
|
|
void LegicRfInfo(void) {
|
|
|
|
// configure ARM and FPGA
|
|
|
|
init_reader(false);
|
|
|
|
|
|
|
|
// establish shared secret and detect card type
|
|
|
|
uint8_t card_type = setup_phase_reader(0x01);
|
|
|
|
if(init_card(card_type, &card) != 0) {
|
|
|
|
cmd_send(CMD_ACK, 0, 0, 0, 0, 0);
|
|
|
|
goto OUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
// read UID
|
|
|
|
for(uint8_t i = 0; i < sizeof(card.uid); ++i) {
|
|
|
|
int16_t byte = read_byte(i, card.cmdsize);
|
|
|
|
if(byte == -1) {
|
|
|
|
cmd_send(CMD_ACK, 0, 0, 0, 0, 0);
|
|
|
|
goto OUT;
|
|
|
|
}
|
|
|
|
card.uid[i] = byte & 0xFF;
|
|
|
|
}
|
|
|
|
|
|
|
|
// read MCC and check against UID
|
|
|
|
int16_t mcc = read_byte(4, card.cmdsize);
|
|
|
|
int16_t calc_mcc = CRC8Legic(card.uid, 4);;
|
|
|
|
if(mcc != calc_mcc) {
|
|
|
|
cmd_send(CMD_ACK, 0, 0, 0, 0, 0);
|
|
|
|
goto OUT;
|
|
|
|
}
|
2016-10-07 01:13:23 +08:00
|
|
|
|
2018-07-29 18:18:08 +08:00
|
|
|
// OK
|
|
|
|
cmd_send(CMD_ACK, 1, 0, 0, (uint8_t*)&card, sizeof(legic_card_select_t));
|
2016-10-05 23:10:29 +08:00
|
|
|
|
2016-09-29 18:23:09 +08:00
|
|
|
OUT:
|
2018-07-29 18:18:08 +08:00
|
|
|
switch_off();
|
2016-09-27 02:01:23 +08:00
|
|
|
}
|
|
|
|
|
2018-07-29 18:18:08 +08:00
|
|
|
void LegicRfReader(uint16_t offset, uint16_t len, uint8_t iv) {
|
|
|
|
// configure ARM and FPGA
|
|
|
|
init_reader(false);
|
|
|
|
|
|
|
|
// establish shared secret and detect card type
|
|
|
|
uint8_t card_type = setup_phase_reader(iv);
|
|
|
|
if(init_card(card_type, &card) != 0) {
|
|
|
|
cmd_send(CMD_ACK, 0, 0, 0, 0, 0);
|
|
|
|
goto OUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
// do not read beyond card memory
|
|
|
|
if(len + offset > card.cardsize) {
|
|
|
|
len = card.cardsize - offset;
|
|
|
|
}
|
|
|
|
|
|
|
|
for(uint16_t i = 0; i < len; ++i) {
|
|
|
|
int16_t byte = read_byte(offset + i, card.cmdsize);
|
|
|
|
if(byte == -1) {
|
|
|
|
cmd_send(CMD_ACK, 0, 0, 0, 0, 0);
|
|
|
|
goto OUT;
|
|
|
|
}
|
|
|
|
legic_mem[i] = byte;
|
|
|
|
}
|
|
|
|
|
|
|
|
// OK
|
|
|
|
cmd_send(CMD_ACK, 1, len, 0, legic_mem, len);
|
2010-05-06 19:24:01 +08:00
|
|
|
|
2018-07-29 18:18:08 +08:00
|
|
|
OUT:
|
|
|
|
switch_off();
|
2010-05-06 19:24:01 +08:00
|
|
|
}
|
|
|
|
|
2018-07-29 18:18:08 +08:00
|
|
|
void LegicRfWriter(uint16_t offset, uint16_t len, uint8_t iv, uint8_t *data) {
|
|
|
|
cmd_send(CMD_ACK, 0, 0, 0, 0, 0); //TODO Implement
|
2016-10-11 03:52:58 +08:00
|
|
|
}
|
2016-10-07 06:15:47 +08:00
|
|
|
|
2018-07-29 18:07:54 +08:00
|
|
|
void LegicRfSimulate(int phase, int frame, int reqresp) {
|
|
|
|
cmd_send(CMD_ACK, 0, 0, 0, 0, 0); //TODO Implement
|
2016-09-02 22:25:54 +08:00
|
|
|
}
|