mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2025-02-13 02:34:48 +08:00
change: remove dead legic code
This code was either disabled or never reached.
This commit is contained in:
Andreas Dröscher
parent
37867fbf3b
commit
33eb2f5fa0
1 changed files with 1 additions and 761 deletions
762
armsrc/legicrf.c
762
armsrc/legicrf.c
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@ -30,43 +30,8 @@ static int legic_phase_drift;
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static int legic_frame_drift;
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static int legic_reqresp_drift;
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AT91PS_TC timer;
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AT91PS_TC prng_timer;
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/*
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static void setup_timer(void) {
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// Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging
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// this it won't be terribly accurate but should be good enough.
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//
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AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
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timer = AT91C_BASE_TC1;
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timer->TC_CCR = AT91C_TC_CLKDIS;
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timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK;
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timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
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//
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// Set up Timer 2 to use for measuring time between frames in
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// tag simulation mode. Runs 4x faster as Timer 1
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//
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AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC2);
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prng_timer = AT91C_BASE_TC2;
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prng_timer->TC_CCR = AT91C_TC_CLKDIS;
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prng_timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV2_CLOCK;
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prng_timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
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}
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AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
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AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
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// fast clock
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
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AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks
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AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
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AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
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AT91C_BASE_TC0->TC_RA = 1;
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AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
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*/
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// At TIMER_CLOCK3 (MCK/32)
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// testing calculating in ticks. 1.5ticks = 1us
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@ -126,20 +91,9 @@ static void frame_clean(struct legic_frame * const f) {
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f->bits = 0;
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}
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// Prng works when waiting in 99.1us cycles.
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// and while sending/receiving in bit frames (100, 60)
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/*static void CalibratePrng( uint32_t time){
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// Calculate Cycles based on timer 100us
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uint32_t i = (time - sendFrameStop) / 100 ;
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// substract cycles of finished frames
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int k = i - legic_prng_count()+1;
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// substract current frame length, rewind to beginning
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if ( k > 0 )
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legic_prng_forward(k);
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}
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*/
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/* Generate Keystream */
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uint32_t get_key_stream(int skip, int count) {
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@ -575,36 +529,7 @@ int legic_select_card(legic_card_select_t *p_card){
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}
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//-----------------------------------------------------------------------------
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// Work with emulator memory
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//
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// Note: we call FpgaDownloadAndGo(FPGA_BITSTREAM_HF) here although FPGA is not
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// involved in dealing with emulator memory. But if it is called later, it might
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// destroy the Emulator Memory.
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//-----------------------------------------------------------------------------
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// arg0 = offset
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// arg1 = num of bytes
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void LegicEMemSet(uint32_t arg0, uint32_t arg1, uint8_t *data) {
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FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
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legic_emlset_mem(data, arg0, arg1);
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}
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// arg0 = offset
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// arg1 = num of bytes
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void LegicEMemGet(uint32_t arg0, uint32_t arg1) {
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FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
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uint8_t buf[USB_CMD_DATA_SIZE] = {0x00};
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legic_emlget_mem(buf, arg0, arg1);
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LED_B_ON();
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cmd_send(CMD_ACK, arg0, arg1, 0, buf, USB_CMD_DATA_SIZE);
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LED_B_OFF();
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}
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void legic_emlset_mem(uint8_t *data, int offset, int numofbytes) {
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cardmem = BigBuf_get_EM_addr();
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memcpy(cardmem + offset, data, numofbytes);
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}
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void legic_emlget_mem(uint8_t *data, int offset, int numofbytes) {
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cardmem = BigBuf_get_EM_addr();
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memcpy(data, cardmem + offset, numofbytes);
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}
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void LegicRfInfo(void){
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@ -932,691 +857,6 @@ void LegicRfSimulate(int phase, int frame, int reqresp)
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LEDsoff();
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cmd_send(CMD_ACK, 1, 0, 0, 0, 0);
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}
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//-----------------------------------------------------------------------------
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// Code up a string of octets at layer 2 (including CRC, we don't generate
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// that here) so that they can be transmitted to the reader. Doesn't transmit
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// them yet, just leaves them ready to send in ToSend[].
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//-----------------------------------------------------------------------------
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// static void CodeLegicAsTag(const uint8_t *cmd, int len)
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// {
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// int i;
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// ToSendReset();
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// // Transmit a burst of ones, as the initial thing that lets the
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// // reader get phase sync. This (TR1) must be > 80/fs, per spec,
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// // but tag that I've tried (a Paypass) exceeds that by a fair bit,
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// // so I will too.
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// for(i = 0; i < 20; i++) {
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// ToSendStuffBit(1);
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// ToSendStuffBit(1);
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// ToSendStuffBit(1);
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// ToSendStuffBit(1);
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// }
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// // Send SOF.
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// for(i = 0; i < 10; i++) {
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// ToSendStuffBit(0);
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// ToSendStuffBit(0);
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// ToSendStuffBit(0);
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// ToSendStuffBit(0);
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// }
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// for(i = 0; i < 2; i++) {
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// ToSendStuffBit(1);
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// ToSendStuffBit(1);
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// ToSendStuffBit(1);
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// ToSendStuffBit(1);
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// }
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// for(i = 0; i < len; i++) {
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// int j;
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// uint8_t b = cmd[i];
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// // Start bit
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// ToSendStuffBit(0);
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// ToSendStuffBit(0);
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// ToSendStuffBit(0);
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// ToSendStuffBit(0);
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// // Data bits
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// for(j = 0; j < 8; j++) {
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// if(b & 1) {
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// ToSendStuffBit(1);
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// ToSendStuffBit(1);
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// ToSendStuffBit(1);
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// ToSendStuffBit(1);
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// } else {
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// ToSendStuffBit(0);
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// ToSendStuffBit(0);
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// ToSendStuffBit(0);
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// ToSendStuffBit(0);
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// }
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// b >>= 1;
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// }
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// // Stop bit
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// ToSendStuffBit(1);
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// ToSendStuffBit(1);
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// ToSendStuffBit(1);
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// ToSendStuffBit(1);
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// }
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// // Send EOF.
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// for(i = 0; i < 10; i++) {
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// ToSendStuffBit(0);
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// ToSendStuffBit(0);
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// ToSendStuffBit(0);
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// ToSendStuffBit(0);
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// }
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// for(i = 0; i < 2; i++) {
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// ToSendStuffBit(1);
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// ToSendStuffBit(1);
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// ToSendStuffBit(1);
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// ToSendStuffBit(1);
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// }
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// // Convert from last byte pos to length
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// ToSendMax++;
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// }
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//-----------------------------------------------------------------------------
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// The software UART that receives commands from the reader, and its state
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// variables.
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//-----------------------------------------------------------------------------
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/*
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static struct {
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enum {
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STATE_UNSYNCD,
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STATE_GOT_FALLING_EDGE_OF_SOF,
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STATE_AWAITING_START_BIT,
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STATE_RECEIVING_DATA
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} state;
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uint16_t shiftReg;
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int bitCnt;
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int byteCnt;
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int byteCntMax;
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int posCnt;
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uint8_t *output;
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} Uart;
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*/
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/* Receive & handle a bit coming from the reader.
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*
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* This function is called 4 times per bit (every 2 subcarrier cycles).
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* Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
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*
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* LED handling:
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* LED A -> ON once we have received the SOF and are expecting the rest.
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* LED A -> OFF once we have received EOF or are in error state or unsynced
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*
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* Returns: true if we received a EOF
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* false if we are still waiting for some more
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*/
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// static RAMFUNC int HandleLegicUartBit(uint8_t bit)
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// {
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// switch(Uart.state) {
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// case STATE_UNSYNCD:
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// if(!bit) {
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// // we went low, so this could be the beginning of an SOF
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// Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
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// Uart.posCnt = 0;
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// Uart.bitCnt = 0;
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// }
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// break;
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// case STATE_GOT_FALLING_EDGE_OF_SOF:
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// Uart.posCnt++;
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// if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
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// if(bit) {
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// if(Uart.bitCnt > 9) {
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// // we've seen enough consecutive
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// // zeros that it's a valid SOF
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// Uart.posCnt = 0;
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// Uart.byteCnt = 0;
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// Uart.state = STATE_AWAITING_START_BIT;
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// LED_A_ON(); // Indicate we got a valid SOF
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// } else {
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// // didn't stay down long enough
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// // before going high, error
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// Uart.state = STATE_UNSYNCD;
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// }
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// } else {
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// // do nothing, keep waiting
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// }
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// Uart.bitCnt++;
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// }
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// if(Uart.posCnt >= 4) Uart.posCnt = 0;
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// if(Uart.bitCnt > 12) {
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// // Give up if we see too many zeros without
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// // a one, too.
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// LED_A_OFF();
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// Uart.state = STATE_UNSYNCD;
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// }
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// break;
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// case STATE_AWAITING_START_BIT:
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// Uart.posCnt++;
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// if(bit) {
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// if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
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// // stayed high for too long between
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// // characters, error
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// Uart.state = STATE_UNSYNCD;
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// }
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// } else {
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// // falling edge, this starts the data byte
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// Uart.posCnt = 0;
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// Uart.bitCnt = 0;
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// Uart.shiftReg = 0;
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// Uart.state = STATE_RECEIVING_DATA;
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// }
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// break;
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// case STATE_RECEIVING_DATA:
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// Uart.posCnt++;
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// if(Uart.posCnt == 2) {
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// // time to sample a bit
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// Uart.shiftReg >>= 1;
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// if(bit) {
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// Uart.shiftReg |= 0x200;
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// }
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// Uart.bitCnt++;
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// }
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// if(Uart.posCnt >= 4) {
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// Uart.posCnt = 0;
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// }
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// if(Uart.bitCnt == 10) {
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// if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
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// {
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// // this is a data byte, with correct
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// // start and stop bits
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// Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
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// Uart.byteCnt++;
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// if(Uart.byteCnt >= Uart.byteCntMax) {
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// // Buffer overflowed, give up
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// LED_A_OFF();
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// Uart.state = STATE_UNSYNCD;
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// } else {
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// // so get the next byte now
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// Uart.posCnt = 0;
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// Uart.state = STATE_AWAITING_START_BIT;
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// }
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// } else if (Uart.shiftReg == 0x000) {
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// // this is an EOF byte
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// LED_A_OFF(); // Finished receiving
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// Uart.state = STATE_UNSYNCD;
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// if (Uart.byteCnt != 0) {
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// return TRUE;
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// }
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// } else {
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// // this is an error
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// LED_A_OFF();
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// Uart.state = STATE_UNSYNCD;
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// }
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// }
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// break;
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// default:
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// LED_A_OFF();
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// Uart.state = STATE_UNSYNCD;
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// break;
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// }
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// return false;
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// }
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/*
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static void UartReset() {
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Uart.byteCntMax = 3;
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Uart.state = STATE_UNSYNCD;
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Uart.byteCnt = 0;
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Uart.bitCnt = 0;
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Uart.posCnt = 0;
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memset(Uart.output, 0x00, 3);
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}
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*/
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// static void UartInit(uint8_t *data) {
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// Uart.output = data;
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// UartReset();
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// }
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//=============================================================================
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// An LEGIC reader. We take layer two commands, code them
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// appropriately, and then send them to the tag. We then listen for the
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// tag's response, which we leave in the buffer to be demodulated on the
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// PC side.
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//=============================================================================
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/*
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static struct {
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enum {
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DEMOD_UNSYNCD,
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DEMOD_PHASE_REF_TRAINING,
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DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
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DEMOD_GOT_FALLING_EDGE_OF_SOF,
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DEMOD_AWAITING_START_BIT,
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DEMOD_RECEIVING_DATA
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} state;
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int bitCount;
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int posCount;
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int thisBit;
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uint16_t shiftReg;
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uint8_t *output;
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int len;
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int sumI;
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int sumQ;
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} Demod;
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*/
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/*
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* Handles reception of a bit from the tag
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*
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* This function is called 2 times per bit (every 4 subcarrier cycles).
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* Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
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*
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* LED handling:
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* LED C -> ON once we have received the SOF and are expecting the rest.
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* LED C -> OFF once we have received EOF or are unsynced
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*
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* Returns: true if we received a EOF
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* false if we are still waiting for some more
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*
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*/
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/*
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static RAMFUNC int HandleLegicSamplesDemod(int ci, int cq)
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{
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int v = 0;
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int ai = ABS(ci);
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int aq = ABS(cq);
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int halfci = (ai >> 1);
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int halfcq = (aq >> 1);
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switch(Demod.state) {
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case DEMOD_UNSYNCD:
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CHECK_FOR_SUBCARRIER()
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if(v > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected
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Demod.state = DEMOD_PHASE_REF_TRAINING;
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Demod.sumI = ci;
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Demod.sumQ = cq;
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Demod.posCount = 1;
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}
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break;
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case DEMOD_PHASE_REF_TRAINING:
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if(Demod.posCount < 8) {
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CHECK_FOR_SUBCARRIER()
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if (v > SUBCARRIER_DETECT_THRESHOLD) {
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// set the reference phase (will code a logic '1') by averaging over 32 1/fs.
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// note: synchronization time > 80 1/fs
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Demod.sumI += ci;
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Demod.sumQ += cq;
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++Demod.posCount;
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} else {
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// subcarrier lost
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Demod.state = DEMOD_UNSYNCD;
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}
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} else {
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Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;
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}
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break;
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case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
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MAKE_SOFT_DECISION()
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//Dbprintf("ICE: %d %d %d %d %d", v, Demod.sumI, Demod.sumQ, ci, cq );
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// logic '0' detected
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if (v <= 0) {
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Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
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// start of SOF sequence
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Demod.posCount = 0;
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} else {
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// maximum length of TR1 = 200 1/fs
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if(Demod.posCount > 25*2) Demod.state = DEMOD_UNSYNCD;
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}
|
||||
++Demod.posCount;
|
||||
break;
|
||||
|
||||
case DEMOD_GOT_FALLING_EDGE_OF_SOF:
|
||||
++Demod.posCount;
|
||||
|
||||
MAKE_SOFT_DECISION()
|
||||
|
||||
if(v > 0) {
|
||||
// low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
|
||||
if(Demod.posCount < 10*2) {
|
||||
Demod.state = DEMOD_UNSYNCD;
|
||||
} else {
|
||||
LED_C_ON(); // Got SOF
|
||||
Demod.state = DEMOD_AWAITING_START_BIT;
|
||||
Demod.posCount = 0;
|
||||
Demod.len = 0;
|
||||
}
|
||||
} else {
|
||||
// low phase of SOF too long (> 12 etu)
|
||||
if(Demod.posCount > 13*2) {
|
||||
Demod.state = DEMOD_UNSYNCD;
|
||||
LED_C_OFF();
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case DEMOD_AWAITING_START_BIT:
|
||||
++Demod.posCount;
|
||||
|
||||
MAKE_SOFT_DECISION()
|
||||
|
||||
if(v > 0) {
|
||||
// max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
|
||||
if(Demod.posCount > 3*2) {
|
||||
Demod.state = DEMOD_UNSYNCD;
|
||||
LED_C_OFF();
|
||||
}
|
||||
} else {
|
||||
// start bit detected
|
||||
Demod.bitCount = 0;
|
||||
Demod.posCount = 1; // this was the first half
|
||||
Demod.thisBit = v;
|
||||
Demod.shiftReg = 0;
|
||||
Demod.state = DEMOD_RECEIVING_DATA;
|
||||
}
|
||||
break;
|
||||
|
||||
case DEMOD_RECEIVING_DATA:
|
||||
|
||||
MAKE_SOFT_DECISION()
|
||||
|
||||
if(Demod.posCount == 0) {
|
||||
// first half of bit
|
||||
Demod.thisBit = v;
|
||||
Demod.posCount = 1;
|
||||
} else {
|
||||
// second half of bit
|
||||
Demod.thisBit += v;
|
||||
Demod.shiftReg >>= 1;
|
||||
// logic '1'
|
||||
if(Demod.thisBit > 0)
|
||||
Demod.shiftReg |= 0x200;
|
||||
|
||||
++Demod.bitCount;
|
||||
|
||||
if(Demod.bitCount == 10) {
|
||||
|
||||
uint16_t s = Demod.shiftReg;
|
||||
|
||||
if((s & 0x200) && !(s & 0x001)) {
|
||||
// stop bit == '1', start bit == '0'
|
||||
uint8_t b = (s >> 1);
|
||||
Demod.output[Demod.len] = b;
|
||||
++Demod.len;
|
||||
Demod.state = DEMOD_AWAITING_START_BIT;
|
||||
} else {
|
||||
Demod.state = DEMOD_UNSYNCD;
|
||||
LED_C_OFF();
|
||||
|
||||
if(s == 0x000) {
|
||||
// This is EOF (start, stop and all data bits == '0'
|
||||
return true;
|
||||
}
|
||||
}
|
||||
}
|
||||
Demod.posCount = 0;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
Demod.state = DEMOD_UNSYNCD;
|
||||
LED_C_OFF();
|
||||
break;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
*/
|
||||
/*
|
||||
// Clear out the state of the "UART" that receives from the tag.
|
||||
static void DemodReset() {
|
||||
Demod.len = 0;
|
||||
Demod.state = DEMOD_UNSYNCD;
|
||||
Demod.posCount = 0;
|
||||
Demod.sumI = 0;
|
||||
Demod.sumQ = 0;
|
||||
Demod.bitCount = 0;
|
||||
Demod.thisBit = 0;
|
||||
Demod.shiftReg = 0;
|
||||
memset(Demod.output, 0x00, 3);
|
||||
}
|
||||
|
||||
static void DemodInit(uint8_t *data) {
|
||||
Demod.output = data;
|
||||
DemodReset();
|
||||
}
|
||||
*/
|
||||
|
||||
/*
|
||||
* Demodulate the samples we received from the tag, also log to tracebuffer
|
||||
* quiet: set to 'TRUE' to disable debug output
|
||||
*/
|
||||
|
||||
/*
|
||||
#define LEGIC_DMA_BUFFER_SIZE 256
|
||||
|
||||
static void GetSamplesForLegicDemod(int n, bool quiet)
|
||||
{
|
||||
int max = 0;
|
||||
bool gotFrame = false;
|
||||
int lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
|
||||
int ci, cq, samples = 0;
|
||||
|
||||
BigBuf_free();
|
||||
|
||||
// And put the FPGA in the appropriate mode
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_QUARTER_FREQ);
|
||||
|
||||
// The response (tag -> reader) that we're receiving.
|
||||
// Set up the demodulator for tag -> reader responses.
|
||||
DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
|
||||
|
||||
// The DMA buffer, used to stream samples from the FPGA
|
||||
int8_t *dmaBuf = (int8_t*) BigBuf_malloc(LEGIC_DMA_BUFFER_SIZE);
|
||||
int8_t *upTo = dmaBuf;
|
||||
|
||||
// Setup and start DMA.
|
||||
if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, LEGIC_DMA_BUFFER_SIZE) ){
|
||||
if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
|
||||
return;
|
||||
}
|
||||
|
||||
// Signal field is ON with the appropriate LED:
|
||||
LED_D_ON();
|
||||
for(;;) {
|
||||
int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;
|
||||
if(behindBy > max) max = behindBy;
|
||||
|
||||
while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (LEGIC_DMA_BUFFER_SIZE-1)) > 2) {
|
||||
ci = upTo[0];
|
||||
cq = upTo[1];
|
||||
upTo += 2;
|
||||
if(upTo >= dmaBuf + LEGIC_DMA_BUFFER_SIZE) {
|
||||
upTo = dmaBuf;
|
||||
AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
|
||||
AT91C_BASE_PDC_SSC->PDC_RNCR = LEGIC_DMA_BUFFER_SIZE;
|
||||
}
|
||||
lastRxCounter -= 2;
|
||||
if(lastRxCounter <= 0)
|
||||
lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
|
||||
|
||||
samples += 2;
|
||||
|
||||
gotFrame = HandleLegicSamplesDemod(ci , cq );
|
||||
if ( gotFrame )
|
||||
break;
|
||||
}
|
||||
|
||||
if(samples > n || gotFrame)
|
||||
break;
|
||||
}
|
||||
|
||||
FpgaDisableSscDma();
|
||||
|
||||
if (!quiet && Demod.len == 0) {
|
||||
Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d",
|
||||
max,
|
||||
samples,
|
||||
gotFrame,
|
||||
Demod.len,
|
||||
Demod.sumI,
|
||||
Demod.sumQ
|
||||
);
|
||||
}
|
||||
|
||||
//Tracing
|
||||
if (Demod.len > 0) {
|
||||
uint8_t parity[MAX_PARITY_SIZE] = {0x00};
|
||||
LogTrace(Demod.output, Demod.len, 0, 0, parity, false);
|
||||
}
|
||||
}
|
||||
|
||||
*/
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Transmit the command (to the tag) that was placed in ToSend[].
|
||||
//-----------------------------------------------------------------------------
|
||||
/*
|
||||
static void TransmitForLegic(void)
|
||||
{
|
||||
int c;
|
||||
|
||||
FpgaSetupSsc();
|
||||
|
||||
while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY))
|
||||
AT91C_BASE_SSC->SSC_THR = 0xff;
|
||||
|
||||
// Signal field is ON with the appropriate Red LED
|
||||
LED_D_ON();
|
||||
|
||||
// Signal we are transmitting with the Green LED
|
||||
LED_B_ON();
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
|
||||
|
||||
for(c = 0; c < 10;) {
|
||||
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
|
||||
AT91C_BASE_SSC->SSC_THR = 0xff;
|
||||
c++;
|
||||
}
|
||||
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
|
||||
volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
|
||||
(void)r;
|
||||
}
|
||||
WDT_HIT();
|
||||
}
|
||||
|
||||
c = 0;
|
||||
for(;;) {
|
||||
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
|
||||
AT91C_BASE_SSC->SSC_THR = ToSend[c];
|
||||
legic_prng_forward(1); // forward the lfsr
|
||||
c++;
|
||||
if(c >= ToSendMax) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
|
||||
volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
|
||||
(void)r;
|
||||
}
|
||||
WDT_HIT();
|
||||
}
|
||||
LED_B_OFF();
|
||||
}
|
||||
*/
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Code a layer 2 command (string of octets, including CRC) into ToSend[],
|
||||
// so that it is ready to transmit to the tag using TransmitForLegic().
|
||||
//-----------------------------------------------------------------------------
|
||||
/*
|
||||
static void CodeLegicBitsAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
|
||||
{
|
||||
int i, j;
|
||||
uint8_t b;
|
||||
|
||||
ToSendReset();
|
||||
|
||||
// Send SOF
|
||||
for(i = 0; i < 7; i++)
|
||||
ToSendStuffBit(1);
|
||||
|
||||
|
||||
for(i = 0; i < cmdlen; i++) {
|
||||
// Start bit
|
||||
ToSendStuffBit(0);
|
||||
|
||||
// Data bits
|
||||
b = cmd[i];
|
||||
for(j = 0; j < bits; j++) {
|
||||
if(b & 1) {
|
||||
ToSendStuffBit(1);
|
||||
} else {
|
||||
ToSendStuffBit(0);
|
||||
}
|
||||
b >>= 1;
|
||||
}
|
||||
}
|
||||
|
||||
// Convert from last character reference to length
|
||||
++ToSendMax;
|
||||
}
|
||||
*/
|
||||
/**
|
||||
Convenience function to encode, transmit and trace Legic comms
|
||||
**/
|
||||
/*
|
||||
static void CodeAndTransmitLegicAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
|
||||
{
|
||||
CodeLegicBitsAsReader(cmd, cmdlen, bits);
|
||||
TransmitForLegic();
|
||||
if (tracing) {
|
||||
uint8_t parity[1] = {0x00};
|
||||
LogTrace(cmd, cmdlen, 0, 0, parity, true);
|
||||
}
|
||||
}
|
||||
|
||||
*/
|
||||
// Set up LEGIC communication
|
||||
/*
|
||||
void ice_legic_setup() {
|
||||
|
||||
// standard things.
|
||||
FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
|
||||
BigBuf_free(); BigBuf_Clear_ext(false);
|
||||
clear_trace();
|
||||
set_tracing(true);
|
||||
DemodReset();
|
||||
UartReset();
|
||||
|
||||
// Set up the synchronous serial port
|
||||
FpgaSetupSsc();
|
||||
|
||||
// connect Demodulated Signal to ADC:
|
||||
SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
|
||||
|
||||
// Signal field is on with the appropriate LED
|
||||
LED_D_ON();
|
||||
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
|
||||
SpinDelay(20);
|
||||
// Start the timer
|
||||
//StartCountSspClk();
|
||||
|
||||
// initalize CRC
|
||||
crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
|
||||
|
||||
// initalize prng
|
||||
legic_prng_init(0);
|
||||
}
|
||||
*/
|
||||
}
|
||||
Loading…
Reference in a new issue