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33eb2f5fa0
This code was either disabled or never reached.
862 lines
21 KiB
C
862 lines
21 KiB
C
//-----------------------------------------------------------------------------
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// (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
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// 2016 Iceman
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//
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// This code is licensed to you under the terms of the GNU GPL, version 2 or,
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// at your option, any later version. See the LICENSE.txt file for the text of
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// the license.
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//-----------------------------------------------------------------------------
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// LEGIC RF simulation code
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//-----------------------------------------------------------------------------
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#include "legicrf.h"
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static struct legic_frame {
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uint8_t bits;
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uint32_t data;
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} current_frame;
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static enum {
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STATE_DISCON,
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STATE_IV,
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STATE_CON,
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} legic_state;
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static crc_t legic_crc;
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static int legic_read_count;
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static uint32_t legic_prng_bc;
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static uint32_t legic_prng_iv;
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static int legic_phase_drift;
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static int legic_frame_drift;
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static int legic_reqresp_drift;
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// At TIMER_CLOCK3 (MCK/32)
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// testing calculating in ticks. 1.5ticks = 1us
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#define RWD_TIME_1 120 // READER_TIME_PAUSE 20us off, 80us on = 100us 80 * 1.5 == 120ticks
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#define RWD_TIME_0 60 // READER_TIME_PAUSE 20us off, 40us on = 60us 40 * 1.5 == 60ticks
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#define RWD_TIME_PAUSE 30 // 20us == 20 * 1.5 == 30ticks */
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#define TAG_BIT_PERIOD 142 // 100us == 100 * 1.5 == 150ticks
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#define TAG_FRAME_WAIT 495 // 330us from READER frame end to TAG frame start. 330 * 1.5 == 495
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#define RWD_TIME_FUZZ 20 // rather generous 13us, since the peak detector + hysteresis fuzz quite a bit
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#define SIM_DIVISOR 586 /* prng_time/SIM_DIVISOR count prng needs to be forwared */
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#define SIM_SHIFT 900 /* prng_time+SIM_SHIFT shift of delayed start */
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#define OFFSET_LOG 1024
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#define FUZZ_EQUAL(value, target, fuzz) ((value) > ((target)-(fuzz)) && (value) < ((target)+(fuzz)))
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#ifndef SHORT_COIL
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# define SHORT_COIL LOW(GPIO_SSC_DOUT);
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#endif
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#ifndef OPEN_COIL
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# define OPEN_COIL HIGH(GPIO_SSC_DOUT);
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#endif
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#ifndef LINE_IN
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# define LINE_IN AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
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#endif
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// Pause pulse, off in 20us / 30ticks,
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// ONE / ZERO bit pulse,
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// one == 80us / 120ticks
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// zero == 40us / 60ticks
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#ifndef COIL_PULSE
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# define COIL_PULSE(x) \
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do { \
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SHORT_COIL; \
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WaitTicks( (RWD_TIME_PAUSE) ); \
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OPEN_COIL; \
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WaitTicks((x)); \
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} while (0);
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#endif
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// ToDo: define a meaningful maximum size for auth_table. The bigger this is, the lower will be the available memory for traces.
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// Historically it used to be FREE_BUFFER_SIZE, which was 2744.
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#define LEGIC_CARD_MEMSIZE 1024
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static uint8_t* cardmem;
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static void frame_append_bit(struct legic_frame * const f, uint8_t bit) {
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// Overflow, won't happen
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if (f->bits >= 31) return;
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f->data |= (bit << f->bits);
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f->bits++;
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}
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static void frame_clean(struct legic_frame * const f) {
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f->data = 0;
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f->bits = 0;
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}
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}
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/* Generate Keystream */
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uint32_t get_key_stream(int skip, int count) {
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int i;
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// Use int to enlarge timer tc to 32bit
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legic_prng_bc += prng_timer->TC_CV;
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// reset the prng timer.
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/* If skip == -1, forward prng time based */
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if(skip == -1) {
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i = (legic_prng_bc + SIM_SHIFT)/SIM_DIVISOR; /* Calculate Cycles based on timer */
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i -= legic_prng_count(); /* substract cycles of finished frames */
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i -= count; /* substract current frame length, rewind to beginning */
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legic_prng_forward(i);
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} else {
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legic_prng_forward(skip);
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}
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i = (count == 6) ? -1 : legic_read_count;
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/* Generate KeyStream */
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return legic_prng_get_bits(count);
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}
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/* Send a frame in tag mode, the FPGA must have been set up by
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* LegicRfSimulate
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*/
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void frame_send_tag(uint16_t response, uint8_t bits) {
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uint16_t mask = 1;
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/* Bitbang the response */
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SHORT_COIL;
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AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
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AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
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/* TAG_FRAME_WAIT -> shift by 2 */
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legic_prng_forward(3);
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response ^= legic_prng_get_bits(bits);
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/* Wait for the frame start */
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WaitTicks( TAG_FRAME_WAIT );
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for (; mask < BITMASK(bits); mask <<= 1) {
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if (response & mask)
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OPEN_COIL
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else
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SHORT_COIL
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WaitTicks(TAG_BIT_PERIOD);
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}
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SHORT_COIL;
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}
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/* Send a frame in reader mode, the FPGA must have been set up by
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* LegicRfReader
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*/
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void frame_sendAsReader(uint32_t data, uint8_t bits){
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uint32_t starttime = GET_TICKS, send = 0, mask = 1;
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// xor lsfr onto data.
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send = data ^ legic_prng_get_bits(bits);
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for (; mask < BITMASK(bits); mask <<= 1) {
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if (send & mask)
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COIL_PULSE(RWD_TIME_1)
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else
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COIL_PULSE(RWD_TIME_0)
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}
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// Final pause to mark the end of the frame
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COIL_PULSE(0);
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// log
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uint8_t cmdbytes[] = {bits, BYTEx(data,0), BYTEx(data,1), BYTEx(data,2), BYTEx(send,0), BYTEx(send,1), BYTEx(send,2)};
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LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, true);
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}
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/* Receive a frame from the card in reader emulation mode, the FPGA and
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* timer must have been set up by LegicRfReader and frame_sendAsReader.
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*
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* The LEGIC RF protocol from card to reader does not include explicit
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* frame start/stop information or length information. The reader must
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* know beforehand how many bits it wants to receive. (Notably: a card
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* sending a stream of 0-bits is indistinguishable from no card present.)
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*
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* Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but
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* I'm not smart enough to use it. Instead I have patched hi_read_tx to output
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* the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look
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* for edges. Count the edges in each bit interval. If they are approximately
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* 0 this was a 0-bit, if they are approximately equal to the number of edges
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* expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the
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* timer that's still running from frame_sendAsReader in order to get a synchronization
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* with the frame that we just sent.
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*
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* FIXME: Because we're relying on the hysteresis to just do the right thing
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* the range is severely reduced (and you'll probably also need a good antenna).
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* So this should be fixed some time in the future for a proper receiver.
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*/
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static void frame_receiveAsReader(struct legic_frame * const f, uint8_t bits) {
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if ( bits > 32 ) return;
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uint8_t i = bits, edges = 0;
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uint32_t the_bit = 1, next_bit_at = 0, data = 0;
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uint32_t old_level = 0;
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volatile uint32_t level = 0;
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frame_clean(f);
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// calibrate the prng.
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legic_prng_forward(2);
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data = legic_prng_get_bits(bits);
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//FIXED time between sending frame and now listening frame. 330us
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uint32_t starttime = GET_TICKS;
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// its about 9+9 ticks delay from end-send to here.
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WaitTicks( 477 );
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next_bit_at = GET_TICKS + TAG_BIT_PERIOD;
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while ( i-- ){
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edges = 0;
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while ( GET_TICKS < next_bit_at) {
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level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
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if (level != old_level)
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++edges;
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old_level = level;
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}
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next_bit_at += TAG_BIT_PERIOD;
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// We expect 42 edges (ONE)
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if ( edges > 20 )
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data ^= the_bit;
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the_bit <<= 1;
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}
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// output
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f->data = data;
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f->bits = bits;
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// log
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uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1)};
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LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, false);
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}
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// Setup pm3 as a Legic Reader
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static uint32_t setup_phase_reader(uint8_t iv) {
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// Switch on carrier and let the tag charge for 5ms
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HIGH(GPIO_SSC_DOUT);
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WaitUS(5000);
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ResetTicks();
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legic_prng_init(0);
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// send IV handshake
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frame_sendAsReader(iv, 7);
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// tag and reader has same IV.
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legic_prng_init(iv);
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frame_receiveAsReader(¤t_frame, 6);
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// 292us (438t) - fixed delay before sending ack.
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// minus log and stuff 100tick?
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WaitTicks(338);
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legic_prng_forward(3);
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// Send obsfuscated acknowledgment frame.
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// 0x19 = 0x18 MIM22, 0x01 LSB READCMD
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// 0x39 = 0x38 MIM256, MIM1024 0x01 LSB READCMD
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switch ( current_frame.data ) {
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case 0x0D: frame_sendAsReader(0x19, 6); break;
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case 0x1D:
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case 0x3D: frame_sendAsReader(0x39, 6); break;
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default: break;
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}
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legic_prng_forward(2);
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return current_frame.data;
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}
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void LegicCommonInit(bool clear_mem) {
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FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);
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SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
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/* Bitbang the transmitter */
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SHORT_COIL;
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AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
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AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
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AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
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// reserve a cardmem, meaning we can use the tracelog function in bigbuff easier.
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cardmem = BigBuf_get_EM_addr();
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if ( clear_mem )
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memset(cardmem, 0x00, LEGIC_CARD_MEMSIZE);
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clear_trace();
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set_tracing(true);
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crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
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StartTicks();
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}
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// Switch off carrier, make sure tag is reset
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static void switch_off_tag_rwd(void) {
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SHORT_COIL;
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WaitUS(20);
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WDT_HIT();
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}
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// calculate crc4 for a legic READ command
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static uint32_t legic4Crc(uint8_t cmd, uint16_t byte_index, uint8_t value, uint8_t cmd_sz) {
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crc_clear(&legic_crc);
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uint32_t temp = (value << cmd_sz) | (byte_index << 1) | cmd;
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crc_update(&legic_crc, temp, cmd_sz + 8 );
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return crc_finish(&legic_crc);
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}
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int legic_read_byte( uint16_t index, uint8_t cmd_sz) {
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uint8_t byte, crc, calcCrc = 0;
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uint32_t cmd = (index << 1) | LEGIC_READ;
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// 90ticks = 60us (should be 100us but crc calc takes time.)
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//WaitTicks(330); // 330ticks prng(4) - works
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WaitTicks(240); // 240ticks prng(3) - works
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frame_sendAsReader(cmd, cmd_sz);
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frame_receiveAsReader(¤t_frame, 12);
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// CRC check.
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byte = BYTEx(current_frame.data, 0);
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crc = BYTEx(current_frame.data, 1);
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calcCrc = legic4Crc(LEGIC_READ, index, byte, cmd_sz);
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if( calcCrc != crc ) {
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Dbprintf("!!! crc mismatch: %x != %x !!!", calcCrc, crc);
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return -1;
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}
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legic_prng_forward(3);
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return byte;
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}
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/*
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* - assemble a write_cmd_frame with crc and send it
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* - wait until the tag sends back an ACK ('1' bit unencrypted)
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* - forward the prng based on the timing
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*/
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bool legic_write_byte(uint16_t index, uint8_t byte, uint8_t addr_sz) {
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bool isOK = false;
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int8_t i = 40;
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uint8_t edges = 0;
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uint8_t cmd_sz = addr_sz+1+8+4; //crc+data+cmd;
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uint32_t steps = 0, next_bit_at, start, crc, old_level = 0;
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crc = legic4Crc(LEGIC_WRITE, index, byte, addr_sz+1);
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// send write command
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uint32_t cmd = LEGIC_WRITE;
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cmd |= index << 1; // index
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cmd |= byte << (addr_sz+1); // Data
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cmd |= (crc & 0xF ) << (addr_sz+1+8); // CRC
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WaitTicks(240);
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frame_sendAsReader(cmd, cmd_sz);
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LINE_IN;
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start = GET_TICKS;
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// ACK, - one single "1" bit after 3.6ms
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// 3.6ms = 3600us * 1.5 = 5400ticks.
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WaitTicks(5400);
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next_bit_at = GET_TICKS + TAG_BIT_PERIOD;
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while ( i-- ) {
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WDT_HIT();
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edges = 0;
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while ( GET_TICKS < next_bit_at) {
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volatile uint32_t level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
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if (level != old_level)
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++edges;
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old_level = level;
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}
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next_bit_at += TAG_BIT_PERIOD;
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// We expect 42 edges (ONE)
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if(edges > 20 ) {
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steps = ( (GET_TICKS - start) / TAG_BIT_PERIOD);
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legic_prng_forward(steps);
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isOK = true;
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goto OUT;
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}
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}
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OUT: ;
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legic_prng_forward(1);
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uint8_t cmdbytes[] = {1, isOK, BYTEx(steps, 0), BYTEx(steps, 1) };
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LogTrace(cmdbytes, sizeof(cmdbytes), start, GET_TICKS, NULL, false);
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return isOK;
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}
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int LegicRfReader(uint16_t offset, uint16_t len, uint8_t iv) {
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uint16_t i = 0;
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uint8_t isOK = 1;
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legic_card_select_t card;
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LegicCommonInit(true);
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if ( legic_select_card_iv(&card, iv) ) {
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isOK = 0;
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goto OUT;
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}
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if (len + offset > card.cardsize)
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len = card.cardsize - offset;
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LED_B_ON();
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while (i < len) {
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int r = legic_read_byte(offset + i, card.cmdsize);
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if (r == -1 || BUTTON_PRESS()) {
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if ( MF_DBGLEVEL >= 2) DbpString("operation aborted");
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isOK = 0;
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goto OUT;
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}
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cardmem[i++] = r;
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WDT_HIT();
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}
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OUT:
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WDT_HIT();
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switch_off_tag_rwd();
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LEDsoff();
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cmd_send(CMD_ACK, isOK, len, 0, cardmem, len);
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return 0;
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}
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void LegicRfWriter(uint16_t offset, uint16_t len, uint8_t iv, uint8_t *data) {
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#define LOWERLIMIT 4
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uint8_t isOK = 1, msg = 0;
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legic_card_select_t card;
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// uid NOT is writeable.
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if ( offset <= LOWERLIMIT ) {
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isOK = 0;
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goto OUT;
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}
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LegicCommonInit(false);
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if ( legic_select_card_iv(&card, iv) ) {
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isOK = 0;
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msg = 1;
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goto OUT;
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}
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if ( len + offset > card.cardsize)
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len = card.cardsize - offset;
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LED_B_ON();
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while( len > 0 ) {
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--len;
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if ( !legic_write_byte( len + offset, data[len], card.addrsize) ) {
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Dbprintf("operation failed | %02X | %02X | %02X", len + offset, len, data[len] );
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isOK = 0;
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goto OUT;
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}
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WDT_HIT();
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}
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OUT:
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cmd_send(CMD_ACK, isOK, msg,0,0,0);
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switch_off_tag_rwd();
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LEDsoff();
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}
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int legic_select_card_iv(legic_card_select_t *p_card, uint8_t iv){
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if ( p_card == NULL ) return 1;
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p_card->tagtype = setup_phase_reader(iv);
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switch(p_card->tagtype) {
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case 0x0d:
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p_card->cmdsize = 6;
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p_card->addrsize = 5;
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p_card->cardsize = 22;
|
|
break;
|
|
case 0x1d:
|
|
p_card->cmdsize = 9;
|
|
p_card->addrsize = 8;
|
|
p_card->cardsize = 256;
|
|
break;
|
|
case 0x3d:
|
|
p_card->cmdsize = 11;
|
|
p_card->addrsize = 10;
|
|
p_card->cardsize = 1024;
|
|
break;
|
|
default:
|
|
p_card->cmdsize = 0;
|
|
p_card->addrsize = 0;
|
|
p_card->cardsize = 0;
|
|
return 2;
|
|
}
|
|
return 0;
|
|
}
|
|
int legic_select_card(legic_card_select_t *p_card){
|
|
return legic_select_card_iv(p_card, 0x01);
|
|
}
|
|
|
|
//-----------------------------------------------------------------------------
|
|
//-----------------------------------------------------------------------------
|
|
|
|
void LegicRfInfo(void){
|
|
|
|
int r;
|
|
|
|
uint8_t buf[sizeof(legic_card_select_t)] = {0x00};
|
|
legic_card_select_t *card = (legic_card_select_t*) buf;
|
|
|
|
LegicCommonInit(false);
|
|
|
|
if ( legic_select_card(card) ) {
|
|
cmd_send(CMD_ACK,0,0,0,0,0);
|
|
goto OUT;
|
|
}
|
|
|
|
// read UID bytes
|
|
for ( uint8_t i = 0; i < sizeof(card->uid); ++i) {
|
|
r = legic_read_byte(i, card->cmdsize);
|
|
if ( r == -1 ) {
|
|
cmd_send(CMD_ACK,0,0,0,0,0);
|
|
goto OUT;
|
|
}
|
|
card->uid[i] = r & 0xFF;
|
|
}
|
|
|
|
// MCC byte.
|
|
r = legic_read_byte(4, card->cmdsize);
|
|
uint32_t calc_mcc = CRC8Legic(card->uid, 4);;
|
|
if ( r != calc_mcc) {
|
|
cmd_send(CMD_ACK,0,0,0,0,0);
|
|
goto OUT;
|
|
}
|
|
|
|
// OK
|
|
cmd_send(CMD_ACK, 1, 0, 0, buf, sizeof(legic_card_select_t));
|
|
|
|
OUT:
|
|
switch_off_tag_rwd();
|
|
LEDsoff();
|
|
}
|
|
|
|
/* Handle (whether to respond) a frame in tag mode
|
|
* Only called when simulating a tag.
|
|
*/
|
|
static void frame_handle_tag(struct legic_frame const * const f)
|
|
{
|
|
// log
|
|
//uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1)};
|
|
//LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, false);
|
|
//Dbprintf("ICE: enter frame_handle_tag: %02x ", f->bits);
|
|
|
|
/* First Part of Handshake (IV) */
|
|
if(f->bits == 7) {
|
|
|
|
LED_C_ON();
|
|
|
|
// Reset prng timer
|
|
//ResetTimer(prng_timer);
|
|
ResetTicks();
|
|
|
|
// IV from reader.
|
|
legic_prng_init(f->data);
|
|
|
|
Dbprintf("ICE: IV: %02x ", f->data);
|
|
|
|
// We should have three tagtypes with three different answers.
|
|
legic_prng_forward(2);
|
|
//frame_send_tag(0x3d, 6); /* MIM1024 0x3d^0x26 = 0x1B */
|
|
frame_send_tag(0x1d, 6); // MIM256
|
|
|
|
legic_state = STATE_IV;
|
|
legic_read_count = 0;
|
|
legic_prng_bc = 0;
|
|
legic_prng_iv = f->data;
|
|
|
|
//ResetTimer(timer);
|
|
//WaitUS(280);
|
|
WaitTicks(388);
|
|
return;
|
|
}
|
|
|
|
/* 0x19==??? */
|
|
if(legic_state == STATE_IV) {
|
|
uint32_t local_key = get_key_stream(3, 6);
|
|
int xored = 0x39 ^ local_key;
|
|
if((f->bits == 6) && (f->data == xored)) {
|
|
legic_state = STATE_CON;
|
|
|
|
ResetTimer(timer);
|
|
WaitTicks(300);
|
|
return;
|
|
|
|
} else {
|
|
legic_state = STATE_DISCON;
|
|
LED_C_OFF();
|
|
Dbprintf("iv: %02x frame: %02x key: %02x xored: %02x", legic_prng_iv, f->data, local_key, xored);
|
|
return;
|
|
}
|
|
}
|
|
|
|
/* Read */
|
|
if(f->bits == 11) {
|
|
if(legic_state == STATE_CON) {
|
|
uint32_t key = get_key_stream(2, 11); //legic_phase_drift, 11);
|
|
uint16_t addr = f->data ^ key;
|
|
addr >>= 1;
|
|
uint8_t data = cardmem[addr];
|
|
|
|
uint32_t crc = legic4Crc(LEGIC_READ, addr, data, 11) << 8;
|
|
|
|
//legic_read_count++;
|
|
//legic_prng_forward(legic_reqresp_drift);
|
|
|
|
frame_send_tag(crc | data, 12);
|
|
//ResetTimer(timer);
|
|
legic_prng_forward(2);
|
|
WaitTicks(330);
|
|
return;
|
|
}
|
|
}
|
|
|
|
/* Write */
|
|
if (f->bits == 23 || f->bits == 21 ) {
|
|
uint32_t key = get_key_stream(-1, 23); //legic_frame_drift, 23);
|
|
uint16_t addr = f->data ^ key;
|
|
addr >>= 1;
|
|
addr &= 0x3ff;
|
|
uint32_t data = f->data ^ key;
|
|
data >>= 11;
|
|
data &= 0xff;
|
|
|
|
cardmem[addr] = data;
|
|
/* write command */
|
|
legic_state = STATE_DISCON;
|
|
LED_C_OFF();
|
|
Dbprintf("write - addr: %x, data: %x", addr, data);
|
|
// should send a ACK after 3.6ms
|
|
return;
|
|
}
|
|
|
|
if(legic_state != STATE_DISCON) {
|
|
Dbprintf("Unexpected: sz:%u, Data:%03.3x, State:%u, Count:%u", f->bits, f->data, legic_state, legic_read_count);
|
|
Dbprintf("IV: %03.3x", legic_prng_iv);
|
|
}
|
|
|
|
legic_state = STATE_DISCON;
|
|
legic_read_count = 0;
|
|
WaitMS(10);
|
|
LED_C_OFF();
|
|
return;
|
|
}
|
|
|
|
/* Read bit by bit untill full frame is received
|
|
* Call to process frame end answer
|
|
*/
|
|
static void emit(int bit) {
|
|
|
|
switch (bit) {
|
|
case 1:
|
|
frame_append_bit(¤t_frame, 1);
|
|
break;
|
|
case 0:
|
|
frame_append_bit(¤t_frame, 0);
|
|
break;
|
|
default:
|
|
if(current_frame.bits <= 4) {
|
|
frame_clean(¤t_frame);
|
|
} else {
|
|
frame_handle_tag(¤t_frame);
|
|
frame_clean(¤t_frame);
|
|
}
|
|
WDT_HIT();
|
|
break;
|
|
}
|
|
}
|
|
|
|
void LegicRfSimulate(int phase, int frame, int reqresp)
|
|
{
|
|
/* ADC path high-frequency peak detector, FPGA in high-frequency simulator mode,
|
|
* modulation mode set to 212kHz subcarrier. We are getting the incoming raw
|
|
* envelope waveform on DIN and should send our response on DOUT.
|
|
*
|
|
* The LEGIC RF protocol is pulse-pause-encoding from reader to card, so we'll
|
|
* measure the time between two rising edges on DIN, and no encoding on the
|
|
* subcarrier from card to reader, so we'll just shift out our verbatim data
|
|
* on DOUT, 1 bit is 100us. The time from reader to card frame is still unclear,
|
|
* seems to be 330us.
|
|
*/
|
|
|
|
int old_level = 0, active = 0;
|
|
volatile int32_t level = 0;
|
|
|
|
legic_state = STATE_DISCON;
|
|
legic_phase_drift = phase;
|
|
legic_frame_drift = frame;
|
|
legic_reqresp_drift = reqresp;
|
|
|
|
|
|
/* to get the stream of bits from FPGA in sim mode.*/
|
|
FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
|
|
// Set up the synchronous serial port
|
|
//FpgaSetupSsc();
|
|
// connect Demodulated Signal to ADC:
|
|
SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
|
|
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_212K);
|
|
//FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_NO_MODULATION);
|
|
|
|
#define LEGIC_DMA_BUFFER 256
|
|
// The DMA buffer, used to stream samples from the FPGA
|
|
//uint8_t *dmaBuf = BigBuf_malloc(LEGIC_DMA_BUFFER);
|
|
//uint8_t *data = dmaBuf;
|
|
// Setup and start DMA.
|
|
// if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, LEGIC_DMA_BUFFER) ){
|
|
// if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
|
|
// return;
|
|
// }
|
|
|
|
//StartCountSspClk();
|
|
/* Bitbang the receiver */
|
|
AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
|
|
AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
|
|
|
|
// need a way to determine which tagtype we are simulating
|
|
|
|
// hook up emulator memory
|
|
cardmem = BigBuf_get_EM_addr();
|
|
|
|
clear_trace();
|
|
set_tracing(true);
|
|
|
|
crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
|
|
|
|
StartTicks();
|
|
|
|
LED_B_ON();
|
|
DbpString("Starting Legic emulator, press button to end");
|
|
|
|
/*
|
|
* The mode FPGA_HF_SIMULATOR_MODULATE_212K works like this.
|
|
* - A 1-bit input to the FPGA becomes 8 pulses on 212kHz (fc/64) (18.88us).
|
|
* - A 0-bit input to the FPGA becomes an unmodulated time of 18.88us
|
|
*
|
|
* In this mode the SOF can be written as 00011101 = 0x1D
|
|
* The EOF can be written as 10111000 = 0xb8
|
|
* A logic 1 is 01
|
|
* A logic 0 is 10
|
|
volatile uint8_t b;
|
|
uint8_t i = 0;
|
|
while( !BUTTON_PRESS() ) {
|
|
WDT_HIT();
|
|
|
|
// not sending anything.
|
|
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
|
|
AT91C_BASE_SSC->SSC_THR = 0x00;
|
|
}
|
|
|
|
// receive
|
|
if ( AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY ) {
|
|
b = (uint8_t) AT91C_BASE_SSC->SSC_RHR;
|
|
bd[i] = b;
|
|
++i;
|
|
// if(OutOfNDecoding(b & 0x0f))
|
|
// *len = Uart.byteCnt;
|
|
}
|
|
|
|
}
|
|
*/
|
|
|
|
while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
|
|
|
|
level = !!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
|
|
|
|
uint32_t time = GET_TICKS;
|
|
|
|
if (level != old_level) {
|
|
if (level == 1) {
|
|
|
|
//Dbprintf("start, %u ", time);
|
|
StartTicks();
|
|
// did we get a signal
|
|
if (FUZZ_EQUAL(time, RWD_TIME_1, RWD_TIME_FUZZ)) {
|
|
// 1 bit
|
|
emit(1);
|
|
active = 1;
|
|
LED_A_ON();
|
|
} else if (FUZZ_EQUAL(time, RWD_TIME_0, RWD_TIME_FUZZ)) {
|
|
// 0 bit
|
|
emit(0);
|
|
active = 1;
|
|
LED_A_ON();
|
|
} else if (active) {
|
|
// invalid
|
|
emit(-1);
|
|
active = 0;
|
|
LED_A_OFF();
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/* Frame end */
|
|
if(time >= (RWD_TIME_1 + RWD_TIME_FUZZ) && active) {
|
|
emit(-1);
|
|
active = 0;
|
|
LED_A_OFF();
|
|
}
|
|
|
|
/*
|
|
* Disable the counter, Then wait for the clock to acknowledge the
|
|
* shutdown in its status register. Reading the SR has the
|
|
* side-effect of clearing any pending state in there.
|
|
*/
|
|
//if(time >= (20*RWD_TIME_1) && (timer->TC_SR & AT91C_TC_CLKSTA))
|
|
if(time >= (20 * RWD_TIME_1) )
|
|
StopTicks();
|
|
|
|
old_level = level;
|
|
WDT_HIT();
|
|
}
|
|
|
|
WDT_HIT();
|
|
DbpString("LEGIC Prime emulator stopped");
|
|
switch_off_tag_rwd();
|
|
FpgaDisableSscDma();
|
|
LEDsoff();
|
|
cmd_send(CMD_ACK, 1, 0, 0, 0, 0);
|
|
}
|
|
}
|
|
|
|
} |