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CHG: FeliCa and 14b/15 enhancements. or it should be atleast. Until it gets tested..

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This commit is contained in:
iceman1001 2017-10-24 18:24:30 +02:00
parent 52eaa3dfe6
commit c2444a885b
3 changed files with 14 additions and 2 deletions
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fpga/fpga_hf.bit
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fpga/fpga_lf.bit
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16
fpga/hi_read_tx.v
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@ -12,7 +12,7 @@ module hi_read_tx(
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
shallow_modulation
shallow_modulation, speed, power
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
@ -23,6 +23,8 @@ module hi_read_tx(
input cross_hi, cross_lo;
output dbg;
input shallow_modulation;
input [1:0] speed;
input power;
// low frequency outputs, not relevant
assign pwr_lo = 1'b0;
@ -36,6 +38,8 @@ reg pwr_oe3;
reg pwr_oe4;
always @(ck_1356megb or ssp_dout or shallow_modulation)
begin
if (power)
begin
if(shallow_modulation)
begin
@ -52,6 +56,14 @@ begin
pwr_oe4 <= 1'b0;
end
end
else
begin
pwr_hi <= 1'b0;
pwr_oe1 <= 1'b0;
pwr_oe3 <= 1'b0;
pwr_oe4 <= ~ssp_dout;
end
end
// Then just divide the 13.56 MHz clock down to produce appropriate clocks
@ -62,7 +74,7 @@ reg [6:0] hi_div_by_128;
always @(posedge ck_1356meg)
hi_div_by_128 <= hi_div_by_128 + 1;
assign ssp_clk = hi_div_by_128[6];
assign ssp_clk = speed[1]? (speed[0]? hi_div_by_128[3]: hi_div_by_128[4]) : (speed[0]? hi_div_by_128[5]: hi_div_by_128[6]);
reg [2:0] hi_byte_div;