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chg: revert it
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parent
29adb88f32
commit
f4409ab375
2 changed files with 3 additions and 9 deletions
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@ -118,7 +118,7 @@ void SetupSpi(int mode) {
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// Set up the synchronous serial port, with the one set of options that we
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// always use when we are talking to the FPGA. Both RX and TX are enabled.
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//-----------------------------------------------------------------------------
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void FpgaSetupSscExt(uint8_t clearPCER) {
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void FpgaSetupSsc(void) {
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// First configure the GPIOs, and get ourselves a clock.
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AT91C_BASE_PIOA->PIO_ASR =
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GPIO_SSC_FRAME |
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@ -127,10 +127,7 @@ void FpgaSetupSscExt(uint8_t clearPCER) {
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GPIO_SSC_CLK;
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AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
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if ( clearPCER )
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AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SSC);
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else
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AT91C_BASE_PMC->PMC_PCER |= (1 << AT91C_ID_SSC);
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// Now set up the SSC proper, starting from a known state.
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AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
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@ -152,9 +149,7 @@ void FpgaSetupSscExt(uint8_t clearPCER) {
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AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
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}
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void FpgaSetupSsc(void) {
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FpgaSetupSscExt(true);
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}
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//-----------------------------------------------------------------------------
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// Set up DMA to receive samples from the FPGA. We will use the PDC, with
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// a single buffer as a circular buffer (so that we just chain back to
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@ -247,7 +242,7 @@ static bool reset_fpga_stream(int bitstream_version, z_streamp compressed_fpga_s
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return false;
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}
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static void DownloadFPGA_byte(unsigned char w) {
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static void DownloadFPGA_byte( uint8_t w) {
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#define SEND_BIT(x) { if(w & (1<<x) ) HIGH(GPIO_FPGA_DIN); else LOW(GPIO_FPGA_DIN); HIGH(GPIO_FPGA_CCLK); LOW(GPIO_FPGA_CCLK); }
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SEND_BIT(7);
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SEND_BIT(6);
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@ -27,7 +27,6 @@ void FpgaSendCommand(uint16_t cmd, uint16_t v);
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void FpgaWriteConfWord(uint8_t v);
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void FpgaDownloadAndGo(int bitstream_version);
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// void FpgaGatherVersion(int bitstream_version, char *dst, int len);
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void FpgaSetupSscExt(uint8_t clearPCER);
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void FpgaSetupSsc(void);
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void SetupSpi(int mode);
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bool FpgaSetupSscDma(uint8_t *buf, int len);
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