Andreas Dröscher
c59150657c
add: xcorr 211.875 kHz option
...
The FPGA supported this frequency for a long time, just the ARM code
had no define to enable it.
2018-08-12 09:59:48 +02:00
Andreas Dröscher
db70ab8f7d
change: remove broken legic simulator
...
It will be rewritten in a later commit
2018-08-12 09:59:48 +02:00
Andreas Dröscher
8a53137ab0
change: remove dead legic code
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This code was either disabled or never reached.
2018-08-12 09:59:48 +02:00
Andreas Dröscher
e779f06c5e
change: clean up Legic interface
...
I see no adventage in poluting all sources that include legicrf.h
with our internal depedencies (includes) and function names.
2018-08-12 09:59:48 +02:00
Iceman
c339035ec5
Revert "WIP: Clean Legic Reader"
2018-08-06 15:05:36 +02:00
Andreas Dröscher
058426fa17
change: added rx/tx coordination timestamp
2018-08-05 00:57:20 +02:00
Andreas Dröscher
8f797d1388
change: legic reader tx back to bigbang
...
I've tried to modulate the Legic specific pause-puls using ssc and the default
ssc clock of 105.4 kHz (bit periode of 9.4us) - previous commit. However,
the timing was not precise enough. By increasing the ssc clock this could
be circumvented, but the adventage over bitbang would be little.
2018-08-05 00:57:20 +02:00
Andreas Dröscher
78d5188922
change: legic reader now uses xcorrelation and ssc based io
...
- Even tough legic tags transmit just AM using xcorrelation
results in a significantly better signal quality.
- Switching from bit bang to a hardware based ssc frees
up CPU time for other tasks e.g. demodulation
2018-08-04 23:13:17 +02:00
Andreas Dröscher
d7c57dbc08
add: xcorr 211.875 kHz option
...
The FPGA supported this frequency for a long time, just the ARM code
had no define to enable it.
2018-08-04 23:13:17 +02:00
Andreas Dröscher
1adff322b1
change: remove broken legic simulator
...
It will be rewritten in a later commit
2018-08-04 23:13:17 +02:00
Andreas Dröscher
33eb2f5fa0
change: remove dead legic code
...
This code was either disabled or never reached.
2018-08-04 23:13:17 +02:00
Andreas Dröscher
37867fbf3b
change: clean up Legic interface
...
I see no adventage in poluting all sources that include legicrf.h
with our internal depedencies (includes) and function names.
2018-08-04 23:13:17 +02:00
Chris
bacf8aff0f
add: FPC connector skeleton usart. Not working but if will be a starting point for those who might want to help out with it.
2018-07-30 09:54:44 +02:00
iceman1001
08d9d9daf9
cleaning
2018-07-29 18:20:56 +02:00
iceman1001
c082531110
fix: potential implicit type cast issue (Thanks to @drandreas for pointing it out)
2018-07-29 18:20:39 +02:00
iceman1001
506da3ff4c
textual
2018-07-29 16:30:36 +02:00
iceman1001
4172ea6c19
cleanup
2018-07-28 14:26:37 +02:00
iceman1001
4d8488e14b
CHG: https://github.com/Proxmark/proxmark3/pull/631 from offical repo. (piwi)
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CHG: textual adjustments
2018-07-28 14:25:12 +02:00
Chris
afeb0d0cd7
fix: removes unneeded floating point lib inclusion (@piwi)
2018-07-23 21:02:13 +02:00
Chris
fff2f51cfb
chg: testing to switch from WaitXX calls to SpinDelay, they seem to mess up
2018-07-06 09:10:13 +02:00
Chris
79158c7360
chg; preparing for more cmds.
2018-07-06 00:24:04 +02:00
Chris
36d774506c
chg: 'sm raw' - implemented 'r' don't read reply
2018-07-05 21:10:21 +02:00
Chris
2ccbde8110
chg: 'flashmem' - adjust debugstatemnts
2018-07-05 20:29:16 +02:00
Chris
fca841122f
chg: 'sc reader' - hooked up atr.
2018-07-05 16:32:10 +02:00
Chris
ee006c6a7b
add: sc upgrade - beta test
2018-07-05 14:38:31 +02:00
Chris
e7342e7402
chg: 'sc upgr' shouldnt print too much
2018-07-05 11:37:04 +02:00
Chris
f70b8be5de
add: 'sc' - smart card commad [rdv40]
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chg: test to read out firmware
2018-07-05 10:48:24 +02:00
Chris
3ecff83de2
chg: clean up
2018-07-04 15:29:27 +02:00
Chris
9571cf1d13
chg: and wrap FPC code with defines..
2018-07-04 13:05:23 +02:00
Chris
a32052b5e6
chg: and remove link to FPC code
2018-07-04 13:01:53 +02:00
Chris
392161e20e
chg: don't compile FPC yet
2018-07-04 12:58:28 +02:00
Chris
8f06f85cc4
DEL: removed old smartcard files
2018-07-04 12:22:12 +02:00
Chris
49735b62f1
syntax sugar
2018-07-04 12:20:08 +02:00
Chris
adb9e94487
chg: OR values
2018-07-04 12:19:29 +02:00
Chris
e09f9cbb32
add: RDV40 smart card module comms ( Thanks to @Willok! ) bitbanging i2c with it
2018-07-04 12:19:04 +02:00
Chris
ed5367a124
chg: adjusting 14b demod to increase reading distance
2018-06-30 22:48:59 +02:00
Chris
2b294912ee
chg: 'hf iclass chk' - enabled credit/debit key selction
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chg: 'hf iclass lookup' - enabled credit/debit key selction
fix: first item in dictionary file now correct identified
chg: code cleanup
2018-06-30 22:47:07 +02:00
Chris
abdd51b6b3
chg: 'hf mf sim' led
2018-06-23 06:31:42 +02:00
Chris
4633e2083a
debug
2018-06-23 06:30:47 +02:00
Chris
28a4260ee9
chg: 14b fixes
2018-06-19 12:57:27 +02:00
Chris
d9e8b63363
chg: setting pins
2018-06-13 14:38:46 +02:00
iceman1001
bd857b263f
syntax
2018-05-22 12:10:02 +02:00
iceman1001
501c29f76d
add: support for reading flashmem
2018-05-22 12:09:17 +02:00
iceman1001
6b7819276d
add: 'mem info' - rudamentary support for new command.
2018-05-06 09:26:06 +02:00
iceman1001
110a7b28cb
chg: 'hf 14a sim' - possibility to simulate FM11RF005SH (@maozhenyu123)
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chg: 'hf 14a info' - tag identification for FM11RF005SH (@maozhenyu123)
Fudan FM11RF005SH , has 512bit mem, 16blocks w 4bytes / block.
Support REQA, READ, WRITE, AUTH. Unknown how the auth is done.
The ATQA/SAK , or a trace from one of these tags would be intersting to look at.
2018-05-06 09:24:28 +02:00
iceman1001
3e7576c86d
fix: 'hf mfu rdbl'
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fix: 'hf mfu dump' - bad exit strategy
2018-05-03 22:41:28 +02:00
iceman1001
4cd72b95c5
fix: coverty scan #277726 , unsigned value comparision always true.
2018-05-03 20:36:01 +02:00
iceman1001
989b80007c
chg: removed debugstatements
2018-05-03 16:20:46 +02:00
iceman1001
e50fef6607
fix: 'mem load' - wrong offset when uploading
2018-05-03 16:10:38 +02:00
iceman1001
021c0a1349
ADD: 'mem' commands. For RDV40 devices only.
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If you don't have one, comment out inside client/Makefile this line
CFLAGS += -DWITH_FLASH
2018-05-03 12:15:03 +02:00
