TC1 counts the number of TC0 overflows (carry bits).
In random conditions TC1 would return or stay at zero,
instead of counting up. This due to the behavior of the
reset signal.
SAM7S Series Datasheet, 33.5.6 Trigger:
Regardless of the trigger used, it will be taken into account
at the following active edge of the selected clock. This means
that the counter value can be read differently from zero just
after a trigger, especially when a low frequency signal is
selected as the clock.
The new code first prepares TC1 and asserts TC1 trigger and
then prepares TC0 and asserts TC0 trigger. The TC0 start-up
will reset TC1.
CHG: TIMER, it turns out the TC0, TC1 and TC2 is only 16bit. So adjust to use two clocks to get a 32bit timer.
CHG: code clean up in legic device side. consistency with variable names..
CHG: 'hf legic read' the device side timings is starting to look much better. HUGE Thanks to @will-rbnt for endless checks and logic analyser feedback. Without his effort this would not work. What does work? We can now use ANY IV in legic. The PM3 Master version is flawed, will only work with IV=0x55.
---still broke--- my crc implementation.. I know I'm about to look into it.
I've added a precise timer in the new files ticks.c and moved some older stuff from util.c to have a solid base for this.
UNTESTED, and the timings measured for t55x7 in lfops.c and other parts has not been adjusted to this "correct" timer.
