iceman1001
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8934fd522d
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fix #833 - missing some configblocks and spelling
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2020-07-08 20:30:53 +02:00 |
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iceman1001
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f4b3dec0c8
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remove verichip.
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2020-07-08 18:09:34 +02:00 |
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iceman1001
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c56245d1aa
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chg 'lf t55xx info' - detection of t55x7 configuration blocks
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2020-07-08 18:04:51 +02:00 |
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iceman1001
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327af5764d
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remove
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2020-07-08 17:37:35 +02:00 |
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iceman1001
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2fcc9b07ef
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disable verichip stuff. should be inside FDX already
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2020-07-08 17:37:01 +02:00 |
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iceman1001
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3fdd4f343b
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textual
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2020-07-08 13:42:37 +02:00 |
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iceman1001
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584fe52153
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lf t55 configblock detection updated
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2020-07-08 13:41:38 +02:00 |
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iceman1001
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b6c7b38ce0
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textual
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2020-07-08 11:11:14 +02:00 |
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iceman1001
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aa0baa26c6
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fix: missing define on some mingw
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2020-07-08 11:09:20 +02:00 |
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iceman1001
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2a30f3b165
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fgpa felica
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2020-07-08 11:05:54 +02:00 |
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iceman1001
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0d4c537ede
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version info for FeliCa fpga image
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2020-07-08 11:05:04 +02:00 |
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iceman1001
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ce24e6acbb
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fpga merge hell, all compiles
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2020-07-08 09:45:49 +02:00 |
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iceman1001
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fef3a764ae
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chg: hf mf decrypt - helptext (thanks @AdamLaurie)
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2020-07-07 15:36:51 +02:00 |
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iceman1001
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b775b68e4e
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fpga iclass
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2020-07-07 13:18:53 +02:00 |
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iceman1001
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2502d4581b
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iclass merges
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2020-07-07 12:32:56 +02:00 |
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iceman1001
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7c15e4b7ff
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fpga more iclass
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2020-07-06 22:43:11 +02:00 |
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iceman1001
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6948ccff3a
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fpga iclass...
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2020-07-06 22:33:38 +02:00 |
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iceman1001
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d83a45f0cb
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fpga merge changes
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2020-07-06 15:16:00 +02:00 |
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Iceman
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ab7c33ecbe
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Update bt_manual_v10.md
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2020-07-06 14:33:13 +02:00 |
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iceman1001
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7811d0a085
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textual
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2020-07-06 05:48:50 +02:00 |
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iceman1001
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7e5b929749
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updated ignore file
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2020-07-06 05:46:46 +02:00 |
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iceman1001
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ae8be54fca
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clean
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2020-07-06 05:43:38 +02:00 |
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iceman1001
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927cd71ed9
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use reflect fct
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2020-07-06 05:43:12 +02:00 |
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iceman1001
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7d3cab1669
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clean
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2020-07-06 05:42:43 +02:00 |
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iceman1001
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791afef728
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adapt reflect8 fct
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2020-07-06 05:42:10 +02:00 |
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iceman1001
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9d204897d1
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fix #830 - 'lf em 4x50_info/read' - now print msb and lsb again.
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2020-07-06 05:41:44 +02:00 |
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Philippe Teuwen
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dfb6b8a69e
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Merge pull request #829 from xianglin1998/master
Android library reused.
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2020-07-05 11:33:30 +02:00 |
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iceman1001
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7d1a278197
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merge hell p.x
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2020-07-03 21:33:17 +02:00 |
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iceman1001
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2c0f595f86
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no more snooping around
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2020-07-03 14:59:10 +02:00 |
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dxl
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64068ba430
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android adapt changed.
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2020-07-03 16:46:40 +08:00 |
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iceman1001
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8189809f48
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chg: adapt to fpga changes
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2020-07-02 12:38:38 +02:00 |
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iceman1001
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80cda059b1
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chg: adapt to fpga changes
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2020-07-02 12:37:07 +02:00 |
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iceman1001
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fce4c1d13f
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chg: adapt to fpga changes
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2020-07-02 12:36:49 +02:00 |
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iceman1001
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837efdf5c4
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chg: adapt to fpga changes
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2020-07-02 12:36:24 +02:00 |
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iceman1001
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4043832c62
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adapt to fpga changes. And bug hunting COTAG functionality that doesnt work
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2020-07-02 12:35:54 +02:00 |
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iceman1001
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ecdd91392b
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adapt to fpga changes. And bug hunting COTAG functionality that doesnt work
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2020-07-02 12:35:33 +02:00 |
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iceman1001
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ee69987210
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chg: third fpga image for felica
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2020-07-02 12:35:24 +02:00 |
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iceman1001
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85053d106f
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adapt to fpga changes. And bug hunting COTAG functionality that doesnt work
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2020-07-02 12:34:48 +02:00 |
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iceman1001
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9130474818
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adaptations to new code
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2020-07-02 12:33:53 +02:00 |
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iceman1001
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2f4335d31e
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chg: ssp clock changes
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2020-07-02 12:33:23 +02:00 |
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iceman1001
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e144c793f0
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chg: scc frames 16 or 8 bit wide
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2020-07-02 12:32:55 +02:00 |
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iceman1001
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e2f0f08202
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added felica bit file
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2020-07-02 11:52:16 +02:00 |
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iceman1001
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fdd0487c37
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updated bit files
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2020-07-02 11:51:52 +02:00 |
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iceman1001
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da947affeb
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felica fpga scr file
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2020-07-02 11:51:07 +02:00 |
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iceman1001
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59836bbb3b
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remove
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2020-07-02 11:50:01 +02:00 |
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iceman1001
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081f397ed7
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remove
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2020-07-02 11:49:46 +02:00 |
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iceman1001
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41dde3281d
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add files
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2020-07-02 11:49:22 +02:00 |
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iceman1001
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8df14408b8
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fgpa changes from official repo. Had to split felica into its own image. Leading to three bit files created.
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2020-07-02 11:47:46 +02:00 |
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DXL
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4e6fef76d0
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Merge pull request #4 from RfidResearchGroup/master
Updated from upstream.
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2020-07-02 16:12:37 +08:00 |
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iceman1001
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e6c046e17c
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adapt banner to smaller views
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2020-07-01 12:31:57 +02:00 |
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