* .h include only the strict minimum for their own parsing
* this forces all files to include explicitment their needs and not count on far streched dependencies
* this helps Makefile to rebuild only the minimum
* according to this rule, most standalone .h are now gone
* big app.h is gone
* remove seldom __cplusplus, if c++ happens, everything will have to be done properly anyway
* all unrequired include were removed
* split common/ into common/ (client+arm) and common_arm/ (os+bootloader)
* bring zlib to common/
* bring stuff not really/not yet used in common back to armsrc/ or client/
* bring liblua into client/
* bring uart into client/
* move some portions of code around (dbprint, protocols,...)
* rename unused files into *_disabled.[ch] to make it explicit
* rename soft Uarts between 14a, 14b and iclass, so a standalone could use several without clash
* remove PrintAndLogDevice
* move deprecated-hid-flasher from client to tools
* Makefiles
* treat deps in armsrc/ as in client/
* client: stop on warning (-Werror), same as for armsrc/
Tested on:
* all standalone modes
* Linux
* SpinDelay and SpinDelayUs: now rounding applies instead of truncating
* Document maximum duration of SpinDelay/SpinDelayUs/BUTTON_CLICK/BUTTON_HELD
* Add argument check against max duration in SpinDelay/BUTTON_CLICK/BUTTON_HELD
* Document why these functions don't need to take wrapping into acount as in GetTickCountDelta
* Use >= in the spinning loops
* Clarify StartTickCount calibration operations and use masks AT91C_CKGR_MAINRDY and AT91C_RTTC_RTPRES
TC1 counts the number of TC0 overflows (carry bits).
In random conditions TC1 would return or stay at zero,
instead of counting up. This due to the behavior of the
reset signal.
SAM7S Series Datasheet, 33.5.6 Trigger:
Regardless of the trigger used, it will be taken into account
at the following active edge of the selected clock. This means
that the counter value can be read differently from zero just
after a trigger, especially when a low frequency signal is
selected as the clock.
The new code first prepares TC1 and asserts TC1 trigger and
then prepares TC0 and asserts TC0 trigger. The TC0 start-up
will reset TC1.
CHG: TIMER, it turns out the TC0, TC1 and TC2 is only 16bit. So adjust to use two clocks to get a 32bit timer.
CHG: code clean up in legic device side. consistency with variable names..
CHG: 'hf legic read' the device side timings is starting to look much better. HUGE Thanks to @will-rbnt for endless checks and logic analyser feedback. Without his effort this would not work. What does work? We can now use ANY IV in legic. The PM3 Master version is flawed, will only work with IV=0x55.
---still broke--- my crc implementation.. I know I'm about to look into it.
I've added a precise timer in the new files ticks.c and moved some older stuff from util.c to have a solid base for this.
UNTESTED, and the timings measured for t55x7 in lfops.c and other parts has not been adjusted to this "correct" timer.
