mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2025-01-07 00:28:07 +08:00
8fcbf652da
+ Add common area at end of RAM to communicate between main os and bootrom + Lower stack end to make room for common area + Implement CMD_DEVICE_INFO in both OS and bootrom to give information about the current state and supported features + Allow hands-free firmware update: When CMD_START_FLASH is received over USB in OS mode, the device will reset and enter the bootrom Pressing the button in hands-free update mode takes precedence: releasing the button will immediately abort firmware update and perform a reset. Do not press the button. + Require each flash sequence to be preceded by a CMD_START_FLASH to set up the boundaries for the following flash sequence Not compatible with linux flasher before SVN revision 200 Currently no compatible flasher for Windows. WINDOWS USERS: DO NOT UPDATE YOUR BOOTROM YET + Protect bootrom flash area unless magic unlock sequence is given in CMD_START_FLASH
286 lines
10 KiB
C
286 lines
10 KiB
C
#include <proxmark3.h>
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struct common_area common_area __attribute__((section(".commonarea")));
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unsigned int start_addr, end_addr, bootrom_unlocked;
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extern char _bootrom_start, _bootrom_end, _flash_start, _flash_end;
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static void ConfigClocks(void)
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{
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// we are using a 16 MHz crystal as the basis for everything
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// slow clock runs at 32Khz typical regardless of crystal
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// enable system clock and USB clock
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PMC_SYS_CLK_ENABLE = PMC_SYS_CLK_PROCESSOR_CLK | PMC_SYS_CLK_UDP_CLK;
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// enable the clock to the following peripherals
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PMC_PERIPHERAL_CLK_ENABLE =
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(1<<PERIPH_PIOA) |
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(1<<PERIPH_ADC) |
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(1<<PERIPH_SPI) |
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(1<<PERIPH_SSC) |
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(1<<PERIPH_PWMC) |
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(1<<PERIPH_UDP);
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// worst case scenario, with 16Mhz xtal startup delay is 14.5ms
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// with a slow clock running at it worst case (max) frequency of 42khz
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// max startup delay = (14.5ms*42k)/8 = 76 = 0x4C round up to 0x50
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// enable main oscillator and set startup delay
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PMC_MAIN_OSCILLATOR = PMC_MAIN_OSCILLATOR_ENABLE |
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PMC_MAIN_OSCILLATOR_STARTUP_DELAY(0x50);
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// wait for main oscillator to stabilize
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while ( !(PMC_INTERRUPT_STATUS & PMC_MAIN_OSCILLATOR_STABILIZED) )
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;
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// minimum PLL clock frequency is 80 MHz in range 00 (96 here so okay)
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// frequency is crystal * multiplier / divisor = 16Mhz * 12 / 2 = 96Mhz
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PMC_PLL = PMC_PLL_DIVISOR(2) | PMC_PLL_COUNT_BEFORE_LOCK(0x50) |
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PMC_PLL_FREQUENCY_RANGE(0) | PMC_PLL_MULTIPLIER(12) |
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PMC_PLL_USB_DIVISOR(1);
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// wait for PLL to lock
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while ( !(PMC_INTERRUPT_STATUS & PMC_MAIN_OSCILLATOR_PLL_LOCK) )
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;
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// we want a master clock (MCK) to be PLL clock / 2 = 96Mhz / 2 = 48Mhz
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// as per datasheet, this register must be programmed in two operations
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// when changing to PLL, program the prescaler first then the source
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PMC_MASTER_CLK = PMC_CLK_PRESCALE_DIV_2;
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// wait for main clock ready signal
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while ( !(PMC_INTERRUPT_STATUS & PMC_MAIN_OSCILLATOR_MCK_READY) )
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;
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// set the source to PLL
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PMC_MASTER_CLK = PMC_CLK_SELECTION_PLL_CLOCK | PMC_CLK_PRESCALE_DIV_2;
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// wait for main clock ready signal
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while ( !(PMC_INTERRUPT_STATUS & PMC_MAIN_OSCILLATOR_MCK_READY) )
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;
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}
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static void Fatal(void)
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{
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for(;;);
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}
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void UsbPacketReceived(BYTE *packet, int len)
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{
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int i, dont_ack=0;
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UsbCommand *c = (UsbCommand *)packet;
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volatile DWORD *p;
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if(len != sizeof(*c)) {
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Fatal();
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}
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switch(c->cmd) {
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case CMD_DEVICE_INFO:
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dont_ack = 1;
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c->cmd = CMD_DEVICE_INFO;
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c->ext1 = DEVICE_INFO_FLAG_BOOTROM_PRESENT | DEVICE_INFO_FLAG_CURRENT_MODE_BOOTROM |
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DEVICE_INFO_FLAG_UNDERSTANDS_START_FLASH;
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if(common_area.flags.osimage_present) c->ext1 |= DEVICE_INFO_FLAG_OSIMAGE_PRESENT;
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UsbSendPacket(packet, len);
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break;
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case CMD_SETUP_WRITE:
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/* The temporary write buffer of the embedded flash controller is mapped to the
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* whole memory region, only the last 8 bits are decoded.
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*/
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p = (volatile DWORD *)&_flash_start;
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for(i = 0; i < 12; i++) {
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p[i+c->ext1] = c->d.asDwords[i];
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}
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break;
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case CMD_FINISH_WRITE:
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p = (volatile DWORD *)&_flash_start;
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for(i = 0; i < 4; i++) {
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p[i+60] = c->d.asDwords[i];
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}
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/* Check that the address that we are supposed to write to is within our allowed region */
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if( ((c->ext1+FLASH_PAGE_SIZE_BYTES-1) >= end_addr) || (c->ext1 < start_addr) ) {
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/* Disallow write */
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dont_ack = 1;
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c->cmd = CMD_NACK;
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UsbSendPacket(packet, len);
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} else {
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/* Translate address to flash page and do flash, update here for the 512k part */
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MC_FLASH_COMMAND = MC_FLASH_COMMAND_KEY |
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MC_FLASH_COMMAND_PAGEN((c->ext1-(int)&_flash_start)/FLASH_PAGE_SIZE_BYTES) |
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FCMD_WRITE_PAGE;
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}
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while(!(MC_FLASH_STATUS & MC_FLASH_STATUS_READY))
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;
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break;
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case CMD_HARDWARE_RESET:
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USB_D_PLUS_PULLUP_OFF();
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RSTC_CONTROL = RST_CONTROL_KEY | RST_CONTROL_PROCESSOR_RESET;
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break;
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case CMD_START_FLASH:
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if(c->ext3 == START_FLASH_MAGIC) bootrom_unlocked = 1;
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else bootrom_unlocked = 0;
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{
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int prot_start = (int)&_bootrom_start;
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int prot_end = (int)&_bootrom_end;
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int allow_start = (int)&_flash_start;
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int allow_end = (int)&_flash_end;
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int cmd_start = c->ext1;
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int cmd_end = c->ext2;
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/* Only allow command if the bootrom is unlocked, or the parameters are outside of the protected
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* bootrom area. In any case they must be within the flash area.
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*/
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if( (bootrom_unlocked || ((cmd_start >= prot_end) || (cmd_end < prot_start)))
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&& (cmd_start >= allow_start) && (cmd_end <= allow_end) ) {
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start_addr = cmd_start;
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end_addr = cmd_end;
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} else {
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start_addr = end_addr = 0;
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dont_ack = 1;
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c->cmd = CMD_NACK;
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UsbSendPacket(packet, len);
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}
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}
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break;
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default:
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Fatal();
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break;
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}
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if(!dont_ack) {
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c->cmd = CMD_ACK;
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UsbSendPacket(packet, len);
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}
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}
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static void flash_mode(int externally_entered)
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{
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start_addr = 0;
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end_addr = 0;
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bootrom_unlocked = 0;
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UsbStart();
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for(;;) {
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WDT_HIT();
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UsbPoll(TRUE);
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if(!externally_entered && !BUTTON_PRESS()) {
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/* Perform a reset to leave flash mode */
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USB_D_PLUS_PULLUP_OFF();
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LED_B_ON();
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RSTC_CONTROL = RST_CONTROL_KEY | RST_CONTROL_PROCESSOR_RESET;
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for(;;);
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}
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if(externally_entered && BUTTON_PRESS()) {
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/* Let the user's button press override the automatic leave */
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externally_entered = 0;
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}
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}
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}
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extern char _osimage_entry;
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void BootROM(void)
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{
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//------------
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// First set up all the I/O pins; GPIOs configured directly, other ones
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// just need to be assigned to the appropriate peripheral.
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// Kill all the pullups, especially the one on USB D+; leave them for
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// the unused pins, though.
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PIO_NO_PULL_UP_ENABLE = (1 << GPIO_USB_PU) |
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(1 << GPIO_LED_A) |
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(1 << GPIO_LED_B) |
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(1 << GPIO_LED_C) |
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(1 << GPIO_LED_D) |
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(1 << GPIO_FPGA_DIN) |
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(1 << GPIO_FPGA_DOUT) |
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(1 << GPIO_FPGA_CCLK) |
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(1 << GPIO_FPGA_NINIT) |
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(1 << GPIO_FPGA_NPROGRAM) |
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(1 << GPIO_FPGA_DONE) |
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(1 << GPIO_MUXSEL_HIPKD) |
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(1 << GPIO_MUXSEL_HIRAW) |
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(1 << GPIO_MUXSEL_LOPKD) |
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(1 << GPIO_MUXSEL_LORAW) |
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(1 << GPIO_RELAY) |
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(1 << GPIO_NVDD_ON);
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// (and add GPIO_FPGA_ON)
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// These pins are outputs
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PIO_OUTPUT_ENABLE = (1 << GPIO_LED_A) |
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(1 << GPIO_LED_B) |
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(1 << GPIO_LED_C) |
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(1 << GPIO_LED_D) |
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(1 << GPIO_RELAY) |
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(1 << GPIO_NVDD_ON);
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// PIO controls the following pins
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PIO_ENABLE = (1 << GPIO_USB_PU) |
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(1 << GPIO_LED_A) |
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(1 << GPIO_LED_B) |
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(1 << GPIO_LED_C) |
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(1 << GPIO_LED_D);
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USB_D_PLUS_PULLUP_OFF();
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LED_D_OFF();
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LED_C_ON();
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LED_B_OFF();
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LED_A_OFF();
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// if 512K FLASH part - TODO make some defines :)
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if ((DBGU_CIDR | 0xf00) == 0xa00) {
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MC_FLASH_MODE0 = MC_FLASH_MODE_FLASH_WAIT_STATES(1) |
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MC_FLASH_MODE_MASTER_CLK_IN_MHZ(0x48);
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MC_FLASH_MODE1 = MC_FLASH_MODE_FLASH_WAIT_STATES(1) |
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MC_FLASH_MODE_MASTER_CLK_IN_MHZ(0x48);
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} else {
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MC_FLASH_MODE0 = MC_FLASH_MODE_FLASH_WAIT_STATES(0) |
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MC_FLASH_MODE_MASTER_CLK_IN_MHZ(48);
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}
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// Initialize all system clocks
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ConfigClocks();
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LED_A_ON();
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int common_area_present = 0;
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switch(RSTC_STATUS & RST_STATUS_TYPE_MASK) {
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case RST_STATUS_TYPE_WATCHDOG:
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case RST_STATUS_TYPE_SOFTWARE:
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case RST_STATUS_TYPE_USER:
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/* In these cases the common_area in RAM should be ok, retain it if it's there */
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if(common_area.magic == COMMON_AREA_MAGIC && common_area.version == 1) {
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common_area_present = 1;
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}
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break;
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default: /* Otherwise, initialize it from scratch */
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break;
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}
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if(!common_area_present){
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/* Common area not ok, initialize it */
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int i; for(i=0; i<sizeof(common_area); i++) { /* Makeshift memset, no need to drag util.c into this */
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((char*)&common_area)[i] = 0;
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}
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common_area.magic = COMMON_AREA_MAGIC;
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common_area.version = 1;
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common_area.flags.bootrom_present = 1;
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}
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common_area.flags.bootrom_present = 1;
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if(common_area.command == COMMON_AREA_COMMAND_ENTER_FLASH_MODE) {
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common_area.command = COMMON_AREA_COMMAND_NONE;
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flash_mode(1);
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} else if(BUTTON_PRESS()) {
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flash_mode(0);
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} else {
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// jump to Flash address of the osimage entry point (LSBit set for thumb mode)
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asm("bx %0\n" : : "r" ( ((int)&_osimage_entry) | 0x1 ) );
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}
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}
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