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51 lines
1 KiB
Verilog
51 lines
1 KiB
Verilog
module hi_sniffer(
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ck_1356meg,
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pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
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adc_d, adc_clk,
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ssp_frame, ssp_din, ssp_clk
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);
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input ck_1356meg;
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output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
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input [7:0] adc_d;
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output adc_clk;
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output ssp_frame, ssp_din, ssp_clk;
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// We are only snooping, all off.
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assign pwr_hi = 1'b0;
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assign pwr_lo = 1'b0;
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assign pwr_oe1 = 1'b0;
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assign pwr_oe2 = 1'b0;
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assign pwr_oe3 = 1'b0;
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assign pwr_oe4 = 1'b0;
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reg ssp_frame;
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reg [7:0] adc_d_out = 8'd0;
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reg [2:0] ssp_cnt = 3'd0;
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assign adc_clk = ck_1356meg;
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assign ssp_clk = ~ck_1356meg;
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always @(posedge ssp_clk)
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begin
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if(ssp_cnt[2:0] == 3'd7)
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ssp_cnt[2:0] <= 3'd0;
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else
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ssp_cnt <= ssp_cnt + 1;
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if(ssp_cnt[2:0] == 3'b000) // set frame length
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begin
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adc_d_out[7:0] <= adc_d;
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ssp_frame <= 1'b1;
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end
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else
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begin
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adc_d_out[7:0] <= {1'b0, adc_d_out[7:1]};
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ssp_frame <= 1'b0;
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end
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end
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assign ssp_din = adc_d_out[0];
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endmodule
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