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tests
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plotedge script: warn for numpy, matplotlib
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2020-02-21 16:10:18 +01:00 |
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clk_divider.v
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style of .v files
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2019-07-30 22:51:38 +02:00 |
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fpga.ucf
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fpga_felica.bit
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Revert "tune stype exceptions"
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2020-08-13 12:48:46 +02:00 |
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fpga_felica.v
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get rid of tabs
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2020-10-06 20:45:13 +02:00 |
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fpga_hf.bit
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Revert "tune stype exceptions"
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2020-08-13 12:48:46 +02:00 |
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fpga_hf.v
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get rid of tabs
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2020-10-06 20:45:13 +02:00 |
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fpga_lf.bit
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Revert "tune stype exceptions"
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2020-08-13 12:48:46 +02:00 |
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fpga_lf.v
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correction of text
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2020-10-01 23:48:32 +02:00 |
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go.bat
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hi_flite.v
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pwr_oe2 is LF
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2020-10-02 19:42:19 +02:00 |
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hi_get_trace.v
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get rid of tabs
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2020-10-06 20:45:13 +02:00 |
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hi_iso14443a.v
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get rid of tabs
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2020-10-06 20:45:13 +02:00 |
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hi_reader.v
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get rid of tabs
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2020-10-06 20:45:13 +02:00 |
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hi_simulate.v
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get rid of tabs
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2020-10-06 20:45:13 +02:00 |
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hi_sniffer.v
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fgpa changes from official repo. Had to split felica into its own image. Leading to three bit files created.
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2020-07-02 11:47:46 +02:00 |
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lf_edge_detect.v
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typos
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2019-08-06 13:51:10 +02:00 |
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lo_adc.v
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assign direct
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2020-01-28 22:06:40 +01:00 |
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lo_edge_detect.v
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style of .v files
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2019-07-30 22:51:38 +02:00 |
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lo_passthru.v
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style of .v files
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2019-07-30 22:51:38 +02:00 |
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lo_read.v
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typos
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2019-08-06 13:51:10 +02:00 |
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lo_simulate.v
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style of .v files
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2019-07-30 22:51:38 +02:00 |
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lp20khz_1MSa_iir_filter.v
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typos
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2019-08-06 13:51:10 +02:00 |
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Makefile
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fgpa changes from official repo. Had to split felica into its own image. Leading to three bit files created.
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2020-07-02 11:47:46 +02:00 |
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min_max_tracker.v
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chg: hitag refactoring (@anon)
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2020-01-01 18:18:34 +01:00 |
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sim.tcl
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testbed_fpga.v
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style of .v files
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2019-07-30 22:51:38 +02:00 |
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testbed_hi_read_tx.v
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typos
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2019-08-06 13:51:10 +02:00 |
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testbed_hi_simulate.v
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typos
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2019-08-06 13:51:10 +02:00 |
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testbed_lo_read.v
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typos
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2019-08-06 13:51:10 +02:00 |
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testbed_lo_simulate.v
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typos
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2019-08-06 13:51:10 +02:00 |
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util.v
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xst_felica.scr
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felica fpga scr file
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2020-07-02 11:51:07 +02:00 |
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xst_hf.scr
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xst_lf.scr
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