iceman1001 8e5a285099 textual		2020-10-02 19:42:47 +02:00
..
tests	plotedge script: warn for numpy, matplotlib	2020-02-21 16:10:18 +01:00
clk_divider.v
fpga.ucf
fpga_felica.bit	Revert "tune stype exceptions"	2020-08-13 12:48:46 +02:00
fpga_felica.v	make style	2020-08-13 12:25:04 +02:00
fpga_hf.bit	Revert "tune stype exceptions"	2020-08-13 12:48:46 +02:00
fpga_hf.v	correction of text	2020-10-01 23:49:01 +02:00
fpga_lf.bit	Revert "tune stype exceptions"	2020-08-13 12:48:46 +02:00
fpga_lf.v	correction of text	2020-10-01 23:48:32 +02:00
go.bat
hi_flite.v	pwr_oe2 is LF	2020-10-02 19:42:19 +02:00
hi_get_trace.v	Add: 'hf plot' - implement function from offical repo (piwi)	2020-01-12 15:33:06 +01:00
hi_iso14443a.v	textual	2020-10-02 19:42:47 +02:00
hi_reader.v	make style	2020-08-13 12:25:04 +02:00
hi_simulate.v	make style	2020-08-13 12:25:04 +02:00
hi_sniffer.v	fgpa changes from official repo. Had to split felica into its own image. Leading to three bit files created.	2020-07-02 11:47:46 +02:00
lf_edge_detect.v
lo_adc.v	assign direct	2020-01-28 22:06:40 +01:00
lo_edge_detect.v
lo_passthru.v
lo_read.v
lo_simulate.v
lp20khz_1MSa_iir_filter.v
Makefile	fgpa changes from official repo. Had to split felica into its own image. Leading to three bit files created.	2020-07-02 11:47:46 +02:00
min_max_tracker.v	chg: hitag refactoring (@anon)	2020-01-01 18:18:34 +01:00
sim.tcl
testbed_fpga.v
testbed_hi_read_tx.v
testbed_hi_simulate.v
testbed_lo_read.v
testbed_lo_simulate.v
util.v
xst_felica.scr	felica fpga scr file	2020-07-02 11:51:07 +02:00
xst_hf.scr
xst_lf.scr