proxmark3/fpga
Philippe Teuwen c03e26cf57 Revert "tune stype exceptions"
This reverts commit aff439953f.
2020-08-13 12:48:46 +02:00
..
tests plotedge script: warn for numpy, matplotlib 2020-02-21 16:10:18 +01:00
clk_divider.v style of .v files 2019-07-30 22:51:38 +02:00
fpga.ucf - improved reader sensitivity for 14443a cards (FPGA change!) 2013-11-19 18:52:40 +00:00
fpga_felica.bit Revert "tune stype exceptions" 2020-08-13 12:48:46 +02:00
fpga_felica.v make style 2020-08-13 12:25:04 +02:00
fpga_hf.bit Revert "tune stype exceptions" 2020-08-13 12:48:46 +02:00
fpga_hf.v make style 2020-08-13 12:25:04 +02:00
fpga_lf.bit Revert "tune stype exceptions" 2020-08-13 12:48:46 +02:00
fpga_lf.v fgpa changes from official repo. Had to split felica into its own image. Leading to three bit files created. 2020-07-02 11:47:46 +02:00
go.bat THIS REQUIRES A BOOTROM UPDATE!! To save FPGA area, split the LF and HF bitstreams and load them on-demand. 2014-06-20 01:02:59 +02:00
hi_flite.v fgpa changes from official repo. Had to split felica into its own image. Leading to three bit files created. 2020-07-02 11:47:46 +02:00
hi_get_trace.v Add: 'hf plot' - implement function from offical repo (piwi) 2020-01-12 15:33:06 +01:00
hi_iso14443a.v make style 2020-08-13 12:25:04 +02:00
hi_reader.v make style 2020-08-13 12:25:04 +02:00
hi_simulate.v make style 2020-08-13 12:25:04 +02:00
hi_sniffer.v fgpa changes from official repo. Had to split felica into its own image. Leading to three bit files created. 2020-07-02 11:47:46 +02:00
lf_edge_detect.v typos 2019-08-06 13:51:10 +02:00
lo_adc.v assign direct 2020-01-28 22:06:40 +01:00
lo_edge_detect.v style of .v files 2019-07-30 22:51:38 +02:00
lo_passthru.v style of .v files 2019-07-30 22:51:38 +02:00
lo_read.v typos 2019-08-06 13:51:10 +02:00
lo_simulate.v style of .v files 2019-07-30 22:51:38 +02:00
lp20khz_1MSa_iir_filter.v typos 2019-08-06 13:51:10 +02:00
Makefile fgpa changes from official repo. Had to split felica into its own image. Leading to three bit files created. 2020-07-02 11:47:46 +02:00
min_max_tracker.v chg: hitag refactoring (@anon) 2020-01-01 18:18:34 +01:00
sim.tcl setting svn:eol-style=native on files, part 3 2010-02-22 19:29:05 +00:00
testbed_fpga.v style of .v files 2019-07-30 22:51:38 +02:00
testbed_hi_read_tx.v typos 2019-08-06 13:51:10 +02:00
testbed_hi_simulate.v typos 2019-08-06 13:51:10 +02:00
testbed_lo_read.v typos 2019-08-06 13:51:10 +02:00
testbed_lo_simulate.v typos 2019-08-06 13:51:10 +02:00
util.v setting svn:eol-style=native on files, part 3 2010-02-22 19:29:05 +00:00
xst_felica.scr felica fpga scr file 2020-07-02 11:51:07 +02:00
xst_hf.scr THIS REQUIRES A BOOTROM UPDATE!! To save FPGA area, split the LF and HF bitstreams and load them on-demand. 2014-06-20 01:02:59 +02:00
xst_lf.scr THIS REQUIRES A BOOTROM UPDATE!! To save FPGA area, split the LF and HF bitstreams and load them on-demand. 2014-06-20 01:02:59 +02:00