2010-02-21 08:12:52 +08:00
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//-----------------------------------------------------------------------------
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// (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
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//
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// This code is licensed to you under the terms of the GNU GPL, version 2 or,
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// at your option, any later version. See the LICENSE.txt file for the text of
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// the license.
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//-----------------------------------------------------------------------------
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// LEGIC RF simulation code
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//-----------------------------------------------------------------------------
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2010-02-21 06:51:00 +08:00
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#include "legicrf.h"
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2010-02-05 16:18:02 +08:00
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2009-10-12 19:47:39 +08:00
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static struct legic_frame {
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2016-09-29 18:23:09 +08:00
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uint8_t bits;
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2010-02-06 17:43:33 +08:00
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uint32_t data;
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2009-10-12 19:47:39 +08:00
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} current_frame;
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2010-02-05 16:18:02 +08:00
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2010-05-06 19:24:01 +08:00
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static enum {
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STATE_DISCON,
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STATE_IV,
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STATE_CON,
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} legic_state;
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static crc_t legic_crc;
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static int legic_read_count;
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static uint32_t legic_prng_bc;
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static uint32_t legic_prng_iv;
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static int legic_phase_drift;
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static int legic_frame_drift;
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static int legic_reqresp_drift;
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2010-02-05 16:18:02 +08:00
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2009-11-05 19:13:46 +08:00
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AT91PS_TC timer;
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2010-05-06 19:24:01 +08:00
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AT91PS_TC prng_timer;
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2009-11-05 19:13:46 +08:00
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2016-09-09 17:56:20 +08:00
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/*
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2016-09-02 22:25:54 +08:00
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static void setup_timer(void) {
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2016-09-09 17:56:20 +08:00
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// Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging
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// this it won't be terribly accurate but should be good enough.
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//
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2009-11-05 19:13:46 +08:00
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AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
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timer = AT91C_BASE_TC1;
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timer->TC_CCR = AT91C_TC_CLKDIS;
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2010-03-04 16:15:59 +08:00
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timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK;
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2009-11-05 19:13:46 +08:00
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timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
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2016-09-09 17:56:20 +08:00
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//
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// Set up Timer 2 to use for measuring time between frames in
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// tag simulation mode. Runs 4x faster as Timer 1
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//
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2010-05-06 19:24:01 +08:00
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AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC2);
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prng_timer = AT91C_BASE_TC2;
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prng_timer->TC_CCR = AT91C_TC_CLKDIS;
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prng_timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV2_CLOCK;
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prng_timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
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}
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2016-09-12 15:19:49 +08:00
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AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
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AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
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// fast clock
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
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AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks
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AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
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AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
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AT91C_BASE_TC0->TC_RA = 1;
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AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
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2016-09-09 17:56:20 +08:00
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*/
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// At TIMER_CLOCK3 (MCK/32)
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2016-09-22 01:03:32 +08:00
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// testing calculating in (us) microseconds.
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2016-09-12 15:19:49 +08:00
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#define RWD_TIME_1 120 // READER_TIME_PAUSE 20us off, 80us on = 100us 80 * 1.5 == 120ticks
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#define RWD_TIME_0 60 // READER_TIME_PAUSE 20us off, 40us on = 60us 40 * 1.5 == 60ticks
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2016-09-11 17:14:12 +08:00
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#define RWD_TIME_PAUSE 30 // 20us == 20 * 1.5 == 30ticks */
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2016-10-04 05:24:59 +08:00
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#define TAG_BIT_PERIOD 144 // 100us == 100 * 1.5 == 150ticks
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2016-09-12 15:19:49 +08:00
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#define TAG_FRAME_WAIT 495 // 330us from READER frame end to TAG frame start. 330 * 1.5 == 495
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2016-09-09 17:56:20 +08:00
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2016-09-11 17:14:12 +08:00
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#define RWD_TIME_FUZZ 20 // rather generous 13us, since the peak detector + hysteresis fuzz quite a bit
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2009-11-05 19:13:46 +08:00
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2010-05-06 19:24:01 +08:00
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#define SIM_DIVISOR 586 /* prng_time/SIM_DIVISOR count prng needs to be forwared */
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#define SIM_SHIFT 900 /* prng_time+SIM_SHIFT shift of delayed start */
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#define OFFSET_LOG 1024
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2009-11-05 19:13:46 +08:00
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#define FUZZ_EQUAL(value, target, fuzz) ((value) > ((target)-(fuzz)) && (value) < ((target)+(fuzz)))
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2009-10-17 06:07:00 +08:00
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2016-09-09 17:56:20 +08:00
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#ifndef SHORT_COIL
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2016-09-11 03:43:08 +08:00
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# define SHORT_COIL LOW(GPIO_SSC_DOUT);
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2016-09-09 17:56:20 +08:00
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#endif
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#ifndef OPEN_COIL
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2016-09-11 03:43:08 +08:00
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# define OPEN_COIL HIGH(GPIO_SSC_DOUT);
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2016-09-09 17:56:20 +08:00
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#endif
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2016-09-12 15:19:49 +08:00
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// Pause pulse, off in 20us / 30ticks,
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// ONE / ZERO bit pulse,
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// one == 80us / 120ticks
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// zero == 40us / 60ticks
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#ifndef COIL_PULSE
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2016-09-24 21:15:24 +08:00
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# define COIL_PULSE(x) \
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do { \
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2016-09-11 17:14:12 +08:00
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SHORT_COIL; \
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2016-09-24 21:15:24 +08:00
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WaitTicks( (RWD_TIME_PAUSE) ); \
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2016-09-11 17:14:12 +08:00
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OPEN_COIL; \
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2016-09-22 01:03:32 +08:00
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WaitTicks((x)); \
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2016-09-24 21:15:24 +08:00
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} while (0)
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2016-09-12 15:19:49 +08:00
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#endif
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2016-09-02 22:25:54 +08:00
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// ToDo: define a meaningful maximum size for auth_table. The bigger this is, the lower will be the available memory for traces.
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// Historically it used to be FREE_BUFFER_SIZE, which was 2744.
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#define LEGIC_CARD_MEMSIZE 1024
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static uint8_t* cardmem;
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2016-09-26 18:26:37 +08:00
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static void frame_append_bit(struct legic_frame * const f, uint8_t bit) {
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2016-09-11 03:43:08 +08:00
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// Overflow, won't happen
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if (f->bits >= 31) return;
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f->data |= (bit << f->bits);
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f->bits++;
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}
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static void frame_clean(struct legic_frame * const f) {
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f->data = 0;
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f->bits = 0;
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}
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2016-09-09 17:56:20 +08:00
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// Prng works when waiting in 99.1us cycles.
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// and while sending/receiving in bit frames (100, 60)
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2016-09-11 03:43:08 +08:00
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/*static void CalibratePrng( uint32_t time){
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2016-09-09 17:56:20 +08:00
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// Calculate Cycles based on timer 100us
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2016-09-14 22:18:04 +08:00
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uint32_t i = (time - sendFrameStop) / 100 ;
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2016-09-09 17:56:20 +08:00
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// substract cycles of finished frames
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int k = i - legic_prng_count()+1;
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// substract current frame length, rewind to beginning
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if ( k > 0 )
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legic_prng_forward(k);
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}
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2016-09-11 03:43:08 +08:00
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*/
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2016-09-09 17:56:20 +08:00
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2010-05-06 19:24:01 +08:00
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/* Generate Keystream */
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2016-09-22 01:03:32 +08:00
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uint32_t get_key_stream(int skip, int count) {
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2016-09-02 22:25:54 +08:00
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uint32_t key = 0;
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int i;
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2015-11-10 04:51:34 +08:00
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2016-09-02 22:25:54 +08:00
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// Use int to enlarge timer tc to 32bit
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2015-11-10 04:51:34 +08:00
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legic_prng_bc += prng_timer->TC_CV;
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2016-09-02 22:25:54 +08:00
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// reset the prng timer.
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2016-09-22 01:03:32 +08:00
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ResetTimer(prng_timer);
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2015-11-10 04:51:34 +08:00
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/* If skip == -1, forward prng time based */
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if(skip == -1) {
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2016-09-02 22:25:54 +08:00
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i = (legic_prng_bc + SIM_SHIFT)/SIM_DIVISOR; /* Calculate Cycles based on timer */
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2015-11-10 04:51:34 +08:00
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i -= legic_prng_count(); /* substract cycles of finished frames */
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2016-09-02 22:25:54 +08:00
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i -= count; /* substract current frame length, rewind to beginning */
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2015-11-10 04:51:34 +08:00
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legic_prng_forward(i);
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} else {
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legic_prng_forward(skip);
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}
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i = (count == 6) ? -1 : legic_read_count;
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2016-09-02 22:25:54 +08:00
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/* Write Time Data into LOG */
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// uint8_t *BigBuf = BigBuf_get_addr();
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// BigBuf[OFFSET_LOG+128+i] = legic_prng_count();
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// BigBuf[OFFSET_LOG+256+i*4] = (legic_prng_bc >> 0) & 0xff;
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// BigBuf[OFFSET_LOG+256+i*4+1] = (legic_prng_bc >> 8) & 0xff;
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// BigBuf[OFFSET_LOG+256+i*4+2] = (legic_prng_bc >>16) & 0xff;
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// BigBuf[OFFSET_LOG+256+i*4+3] = (legic_prng_bc >>24) & 0xff;
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// BigBuf[OFFSET_LOG+384+i] = count;
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2015-11-10 04:51:34 +08:00
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/* Generate KeyStream */
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for(i=0; i<count; i++) {
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key |= legic_prng_get_bit() << i;
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legic_prng_forward(1);
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}
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return key;
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2010-05-06 19:24:01 +08:00
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}
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/* Send a frame in tag mode, the FPGA must have been set up by
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* LegicRfSimulate
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*/
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2016-09-22 01:03:32 +08:00
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void frame_send_tag(uint16_t response, uint8_t bits, uint8_t crypt) {
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2016-09-09 17:56:20 +08:00
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/* Bitbang the response */
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LOW(GPIO_SSC_DOUT);
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AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
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AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
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2010-05-06 19:24:01 +08:00
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2016-09-09 17:56:20 +08:00
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/* Use time to crypt frame */
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if(crypt) {
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2016-09-12 15:19:49 +08:00
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legic_prng_forward(2); /* TAG_FRAME_WAIT -> shift by 2 */
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2016-09-09 17:56:20 +08:00
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response ^= legic_prng_get_bits(bits);
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}
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2016-09-02 22:25:54 +08:00
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2016-09-09 17:56:20 +08:00
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/* Wait for the frame start */
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2016-09-22 01:03:32 +08:00
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WaitUS( TAG_FRAME_WAIT );
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2010-02-21 05:57:20 +08:00
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2016-09-09 17:56:20 +08:00
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uint8_t bit = 0;
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2016-09-03 18:18:02 +08:00
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for(int i = 0; i < bits; i++) {
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2016-09-02 22:25:54 +08:00
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2016-09-09 17:56:20 +08:00
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bit = response & 1;
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response >>= 1;
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2010-02-05 16:18:02 +08:00
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2016-09-09 17:56:20 +08:00
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if (bit)
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HIGH(GPIO_SSC_DOUT);
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2015-11-10 04:51:34 +08:00
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else
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2016-09-09 17:56:20 +08:00
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LOW(GPIO_SSC_DOUT);
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2016-09-22 01:03:32 +08:00
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WaitUS(100);
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2016-09-09 17:56:20 +08:00
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}
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LOW(GPIO_SSC_DOUT);
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}
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2016-09-02 22:25:54 +08:00
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2016-09-09 17:56:20 +08:00
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/* Send a frame in reader mode, the FPGA must have been set up by
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* LegicRfReader
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*/
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2016-09-22 01:03:32 +08:00
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void frame_sendAsReader(uint32_t data, uint8_t bits){
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2016-09-02 22:25:54 +08:00
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2016-09-12 15:19:49 +08:00
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uint32_t starttime = GET_TICKS, send = 0;
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2016-09-09 17:56:20 +08:00
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uint16_t mask = 1;
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2016-09-12 15:19:49 +08:00
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// xor lsfr onto data.
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send = data ^ legic_prng_get_bits(bits);
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2016-09-09 17:56:20 +08:00
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for (; mask < BITMASK(bits); mask <<= 1) {
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2016-09-29 23:43:39 +08:00
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if (send & mask)
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2016-09-11 17:14:12 +08:00
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COIL_PULSE(RWD_TIME_1);
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2016-09-29 23:43:39 +08:00
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else
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2016-09-11 17:14:12 +08:00
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COIL_PULSE(RWD_TIME_0);
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2009-11-06 23:37:53 +08:00
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}
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2010-02-21 05:57:20 +08:00
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2016-09-11 17:14:12 +08:00
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// Final pause to mark the end of the frame
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COIL_PULSE(0);
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2016-09-11 03:43:08 +08:00
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2016-09-29 23:43:39 +08:00
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// log
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uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1), BYTEx(send, 0), BYTEx(send, 1)};
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LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, TRUE);
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2009-11-06 23:37:53 +08:00
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}
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/* Receive a frame from the card in reader emulation mode, the FPGA and
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2016-09-09 17:56:20 +08:00
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* timer must have been set up by LegicRfReader and frame_sendAsReader.
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2010-02-21 05:57:20 +08:00
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*
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2009-11-06 23:37:53 +08:00
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* The LEGIC RF protocol from card to reader does not include explicit
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* frame start/stop information or length information. The reader must
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* know beforehand how many bits it wants to receive. (Notably: a card
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* sending a stream of 0-bits is indistinguishable from no card present.)
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2010-02-21 05:57:20 +08:00
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*
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2009-11-06 23:37:53 +08:00
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* Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but
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* I'm not smart enough to use it. Instead I have patched hi_read_tx to output
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* the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look
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* for edges. Count the edges in each bit interval. If they are approximately
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* 0 this was a 0-bit, if they are approximately equal to the number of edges
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* expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the
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2016-09-09 17:56:20 +08:00
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* timer that's still running from frame_sendAsReader in order to get a synchronization
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2009-11-06 23:37:53 +08:00
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* with the frame that we just sent.
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2010-02-21 05:57:20 +08:00
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*
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* FIXME: Because we're relying on the hysteresis to just do the right thing
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2009-11-06 23:37:53 +08:00
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* the range is severely reduced (and you'll probably also need a good antenna).
|
2010-02-21 05:57:20 +08:00
|
|
|
* So this should be fixed some time in the future for a proper receiver.
|
2009-11-06 23:37:53 +08:00
|
|
|
*/
|
2016-09-12 15:19:49 +08:00
|
|
|
static void frame_receiveAsReader(struct legic_frame * const f, uint8_t bits) {
|
2016-09-09 17:56:20 +08:00
|
|
|
|
2016-09-22 01:03:32 +08:00
|
|
|
if ( bits > 32 ) return;
|
2010-05-06 19:24:01 +08:00
|
|
|
|
2016-09-22 01:03:32 +08:00
|
|
|
uint8_t i = bits, edges = 0;
|
2016-09-29 03:37:08 +08:00
|
|
|
uint32_t the_bit = 1, next_bit_at = 0, data = 0;
|
2016-09-29 23:43:39 +08:00
|
|
|
uint32_t old_level = 0;
|
|
|
|
volatile uint32_t level = 0;
|
2016-09-24 21:15:24 +08:00
|
|
|
|
2016-09-29 23:43:39 +08:00
|
|
|
frame_clean(f);
|
|
|
|
|
2016-09-11 04:47:11 +08:00
|
|
|
AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
|
|
|
|
AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
|
|
|
|
|
2016-09-26 18:26:37 +08:00
|
|
|
// calibrate the prng.
|
2016-09-11 03:43:08 +08:00
|
|
|
legic_prng_forward(2);
|
2016-09-30 03:36:43 +08:00
|
|
|
data = legic_prng_get_bits(bits);
|
2016-09-11 03:43:08 +08:00
|
|
|
|
|
|
|
//FIXED time between sending frame and now listening frame. 330us
|
2016-09-12 15:19:49 +08:00
|
|
|
uint32_t starttime = GET_TICKS;
|
2016-10-04 05:24:59 +08:00
|
|
|
// its about 9+9 ticks delay from end-send to here.
|
|
|
|
//WaitTicks( 495 - 9 - 9 );
|
|
|
|
WaitTicks( 477 );
|
2016-09-26 18:26:37 +08:00
|
|
|
|
2016-09-30 03:36:43 +08:00
|
|
|
next_bit_at = GET_TICKS + TAG_BIT_PERIOD;
|
2016-09-24 21:15:24 +08:00
|
|
|
|
2016-09-22 01:03:32 +08:00
|
|
|
while ( i-- ){
|
2009-11-06 23:37:53 +08:00
|
|
|
edges = 0;
|
2016-09-12 15:19:49 +08:00
|
|
|
while ( GET_TICKS < next_bit_at) {
|
2016-09-09 17:56:20 +08:00
|
|
|
|
2016-09-11 03:43:08 +08:00
|
|
|
level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
|
2016-09-09 17:56:20 +08:00
|
|
|
|
|
|
|
if (level != old_level)
|
2016-09-11 03:43:08 +08:00
|
|
|
++edges;
|
|
|
|
|
2009-11-06 23:37:53 +08:00
|
|
|
old_level = level;
|
2016-09-24 21:15:24 +08:00
|
|
|
}
|
|
|
|
|
2016-09-09 17:56:20 +08:00
|
|
|
next_bit_at += TAG_BIT_PERIOD;
|
2010-05-06 19:24:01 +08:00
|
|
|
|
2016-09-29 23:43:39 +08:00
|
|
|
// We expect 42 edges (ONE)
|
2016-09-26 18:26:37 +08:00
|
|
|
if ( edges > 20 )
|
2010-02-05 16:18:02 +08:00
|
|
|
data ^= the_bit;
|
2016-09-14 22:18:04 +08:00
|
|
|
|
|
|
|
the_bit <<= 1;
|
2009-11-06 23:37:53 +08:00
|
|
|
}
|
2010-02-21 05:57:20 +08:00
|
|
|
|
2016-09-11 03:43:08 +08:00
|
|
|
// output
|
2009-11-06 23:37:53 +08:00
|
|
|
f->data = data;
|
|
|
|
f->bits = bits;
|
2016-09-11 04:47:11 +08:00
|
|
|
|
2016-09-29 23:43:39 +08:00
|
|
|
// log
|
2016-09-29 20:46:12 +08:00
|
|
|
uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1)};
|
2016-09-26 18:26:37 +08:00
|
|
|
LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, FALSE);
|
2009-10-12 19:47:39 +08:00
|
|
|
}
|
|
|
|
|
2016-09-02 22:25:54 +08:00
|
|
|
// Setup pm3 as a Legic Reader
|
2016-09-14 22:18:04 +08:00
|
|
|
static uint32_t setup_phase_reader(uint8_t iv) {
|
2016-09-22 01:03:32 +08:00
|
|
|
|
2016-09-03 18:18:02 +08:00
|
|
|
// Switch on carrier and let the tag charge for 1ms
|
2016-09-09 17:56:20 +08:00
|
|
|
HIGH(GPIO_SSC_DOUT);
|
2016-10-04 06:07:07 +08:00
|
|
|
WaitUS(5000);
|
2016-09-09 17:56:20 +08:00
|
|
|
|
2016-09-22 01:03:32 +08:00
|
|
|
ResetTicks();
|
2016-09-09 17:56:20 +08:00
|
|
|
|
2016-09-03 18:18:02 +08:00
|
|
|
// no keystream yet
|
2016-09-02 22:25:54 +08:00
|
|
|
legic_prng_init(0);
|
2016-09-03 18:18:02 +08:00
|
|
|
|
2016-09-09 17:56:20 +08:00
|
|
|
// send IV handshake
|
|
|
|
frame_sendAsReader(iv, 7);
|
|
|
|
|
|
|
|
// Now both tag and reader has same IV. Prng can start.
|
2010-05-06 19:24:01 +08:00
|
|
|
legic_prng_init(iv);
|
2010-02-21 05:57:20 +08:00
|
|
|
|
2016-09-12 15:19:49 +08:00
|
|
|
frame_receiveAsReader(¤t_frame, 6);
|
2016-09-03 18:18:02 +08:00
|
|
|
|
2016-09-29 03:37:08 +08:00
|
|
|
// 292us (438t) - fixed delay before sending ack.
|
|
|
|
// minus log and stuff 100tick?
|
|
|
|
WaitTicks(338);
|
|
|
|
legic_prng_forward(3);
|
2016-09-09 17:56:20 +08:00
|
|
|
|
2016-09-03 18:18:02 +08:00
|
|
|
// Send obsfuscated acknowledgment frame.
|
2016-09-09 17:56:20 +08:00
|
|
|
// 0x19 = 0x18 MIM22, 0x01 LSB READCMD
|
|
|
|
// 0x39 = 0x38 MIM256, MIM1024 0x01 LSB READCMD
|
|
|
|
switch ( current_frame.data ) {
|
2016-09-14 22:18:04 +08:00
|
|
|
case 0x0D: frame_sendAsReader(0x19, 6); break;
|
|
|
|
case 0x1D:
|
|
|
|
case 0x3D: frame_sendAsReader(0x39, 6); break;
|
|
|
|
default: break;
|
2016-09-03 18:18:02 +08:00
|
|
|
}
|
2016-09-29 03:37:08 +08:00
|
|
|
|
|
|
|
legic_prng_forward(2);
|
2010-02-05 16:18:02 +08:00
|
|
|
return current_frame.data;
|
2009-12-29 02:19:00 +08:00
|
|
|
}
|
|
|
|
|
2016-09-22 01:03:32 +08:00
|
|
|
static void LegicCommonInit(void) {
|
|
|
|
|
2014-06-20 07:02:59 +08:00
|
|
|
FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
|
2016-09-11 03:43:08 +08:00
|
|
|
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);
|
2009-11-06 23:37:53 +08:00
|
|
|
SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
|
2010-02-21 05:57:20 +08:00
|
|
|
|
2009-11-06 23:37:53 +08:00
|
|
|
/* Bitbang the transmitter */
|
2016-09-09 17:56:20 +08:00
|
|
|
LOW(GPIO_SSC_DOUT);
|
2009-11-06 23:37:53 +08:00
|
|
|
AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
|
|
|
|
AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
|
2010-02-21 05:57:20 +08:00
|
|
|
|
2016-09-02 22:25:54 +08:00
|
|
|
// reserve a cardmem, meaning we can use the tracelog function in bigbuff easier.
|
2016-10-04 05:24:59 +08:00
|
|
|
cardmem = BigBuf_get_EM_addr();
|
2016-09-02 22:25:54 +08:00
|
|
|
memset(cardmem, 0x00, LEGIC_CARD_MEMSIZE);
|
|
|
|
|
|
|
|
clear_trace();
|
|
|
|
set_tracing(TRUE);
|
2010-02-05 16:18:02 +08:00
|
|
|
crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
|
2016-09-09 17:56:20 +08:00
|
|
|
|
2016-09-22 01:03:32 +08:00
|
|
|
StartTicks();
|
2010-02-05 16:18:02 +08:00
|
|
|
}
|
|
|
|
|
2016-09-12 15:19:49 +08:00
|
|
|
// Switch off carrier, make sure tag is reset
|
2016-09-02 22:25:54 +08:00
|
|
|
static void switch_off_tag_rwd(void) {
|
2016-09-09 17:56:20 +08:00
|
|
|
LOW(GPIO_SSC_DOUT);
|
2016-09-27 02:01:23 +08:00
|
|
|
WaitUS(20);
|
2010-02-05 16:18:02 +08:00
|
|
|
WDT_HIT();
|
|
|
|
}
|
2016-09-02 22:25:54 +08:00
|
|
|
|
2016-09-03 18:18:02 +08:00
|
|
|
// calculate crc4 for a legic READ command
|
2016-09-29 23:43:39 +08:00
|
|
|
static uint32_t legic4Crc(uint8_t cmd, uint16_t byte_index, uint8_t value, uint8_t cmd_sz) {
|
2016-09-09 17:56:20 +08:00
|
|
|
crc_clear(&legic_crc);
|
2016-09-29 23:43:39 +08:00
|
|
|
uint32_t temp = (value << cmd_sz) | (byte_index << 1) | cmd;
|
2016-09-29 20:46:12 +08:00
|
|
|
crc_update(&legic_crc, temp, cmd_sz + 8 );
|
2010-02-05 16:18:02 +08:00
|
|
|
return crc_finish(&legic_crc);
|
|
|
|
}
|
|
|
|
|
2016-09-29 23:43:39 +08:00
|
|
|
int legic_read_byte( uint16_t index, uint8_t cmd_sz) {
|
2010-02-05 16:18:02 +08:00
|
|
|
|
2016-09-29 23:43:39 +08:00
|
|
|
uint8_t byte, crc, calcCrc = 0;
|
|
|
|
uint32_t cmd = (index << 1) | LEGIC_READ;
|
2016-09-29 20:46:12 +08:00
|
|
|
|
2016-09-30 03:36:43 +08:00
|
|
|
//WaitTicks(366);
|
|
|
|
WaitTicks(330);
|
2016-09-27 02:01:23 +08:00
|
|
|
|
2016-09-09 17:56:20 +08:00
|
|
|
frame_sendAsReader(cmd, cmd_sz);
|
2016-09-12 15:19:49 +08:00
|
|
|
frame_receiveAsReader(¤t_frame, 12);
|
2016-09-02 22:25:54 +08:00
|
|
|
|
2016-09-30 03:36:43 +08:00
|
|
|
// CRC check.
|
2016-09-12 15:19:49 +08:00
|
|
|
byte = BYTEx(current_frame.data, 0);
|
2016-09-29 20:46:12 +08:00
|
|
|
crc = BYTEx(current_frame.data, 1);
|
2016-09-29 23:43:39 +08:00
|
|
|
calcCrc = legic4Crc(LEGIC_READ, index, byte, cmd_sz);
|
2016-01-26 03:19:15 +08:00
|
|
|
|
2016-09-29 20:46:12 +08:00
|
|
|
if( calcCrc != crc ) {
|
|
|
|
Dbprintf("!!! crc mismatch: expected %x but got %x !!!", calcCrc, crc);
|
|
|
|
return -1;
|
|
|
|
}
|
2016-09-29 03:37:08 +08:00
|
|
|
|
|
|
|
legic_prng_forward(4);
|
2010-02-05 16:18:02 +08:00
|
|
|
return byte;
|
|
|
|
}
|
|
|
|
|
2016-09-02 22:25:54 +08:00
|
|
|
/*
|
|
|
|
* - assemble a write_cmd_frame with crc and send it
|
|
|
|
* - wait until the tag sends back an ACK ('1' bit unencrypted)
|
|
|
|
* - forward the prng based on the timing
|
2010-02-05 16:18:02 +08:00
|
|
|
*/
|
2016-07-29 03:41:44 +08:00
|
|
|
//int legic_write_byte(int byte, int addr, int addr_sz, int PrngCorrection) {
|
2016-09-12 15:19:49 +08:00
|
|
|
int legic_write_byte(uint8_t byte, uint16_t addr, uint8_t addr_sz) {
|
2016-09-02 22:25:54 +08:00
|
|
|
|
|
|
|
//do not write UID, CRC at offset 0-4.
|
2016-09-12 15:19:49 +08:00
|
|
|
if (addr <= 4) return 0;
|
2016-09-02 22:25:54 +08:00
|
|
|
|
|
|
|
// crc
|
2010-05-06 19:24:01 +08:00
|
|
|
crc_clear(&legic_crc);
|
|
|
|
crc_update(&legic_crc, 0, 1); /* CMD_WRITE */
|
|
|
|
crc_update(&legic_crc, addr, addr_sz);
|
|
|
|
crc_update(&legic_crc, byte, 8);
|
|
|
|
uint32_t crc = crc_finish(&legic_crc);
|
2016-09-02 22:25:54 +08:00
|
|
|
|
2016-09-12 15:19:49 +08:00
|
|
|
uint32_t crc2 = legic4Crc(LEGIC_WRITE, addr, byte, addr_sz+1);
|
|
|
|
if ( crc != crc2 )
|
|
|
|
Dbprintf("crc is missmatch");
|
|
|
|
|
2016-09-02 22:25:54 +08:00
|
|
|
// send write command
|
2010-05-06 19:24:01 +08:00
|
|
|
uint32_t cmd = ((crc <<(addr_sz+1+8)) //CRC
|
|
|
|
|(byte <<(addr_sz+1)) //Data
|
|
|
|
|(addr <<1) //Address
|
2016-09-12 15:19:49 +08:00
|
|
|
| LEGIC_WRITE); //CMD = Write
|
|
|
|
|
2010-05-06 19:24:01 +08:00
|
|
|
uint32_t cmd_sz = addr_sz+1+8+4; //crc+data+cmd
|
|
|
|
|
2016-08-26 23:17:40 +08:00
|
|
|
legic_prng_forward(2); /* we wait anyways */
|
2016-09-02 22:25:54 +08:00
|
|
|
|
2016-09-22 01:03:32 +08:00
|
|
|
WaitUS(TAG_FRAME_WAIT);
|
2016-09-02 22:25:54 +08:00
|
|
|
|
2016-09-09 17:56:20 +08:00
|
|
|
frame_sendAsReader(cmd, cmd_sz);
|
2016-09-02 22:25:54 +08:00
|
|
|
|
2016-10-04 05:24:59 +08:00
|
|
|
|
2016-09-12 15:19:49 +08:00
|
|
|
AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
|
|
|
|
AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
|
2010-05-06 19:24:01 +08:00
|
|
|
|
2016-09-02 22:25:54 +08:00
|
|
|
// wait for ack
|
|
|
|
int t, old_level = 0, edges = 0;
|
|
|
|
int next_bit_at = 0;
|
2016-07-29 03:41:44 +08:00
|
|
|
|
2016-09-22 01:03:32 +08:00
|
|
|
WaitUS(TAG_FRAME_WAIT);
|
2016-09-02 22:25:54 +08:00
|
|
|
|
2016-09-12 15:19:49 +08:00
|
|
|
for( t = 0; t < 80; ++t) {
|
2010-05-06 19:24:01 +08:00
|
|
|
edges = 0;
|
2016-09-09 17:56:20 +08:00
|
|
|
next_bit_at += TAG_BIT_PERIOD;
|
2010-05-06 19:24:01 +08:00
|
|
|
while(timer->TC_CV < next_bit_at) {
|
2016-10-04 05:24:59 +08:00
|
|
|
volatile uint32_t level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
|
2016-09-12 15:19:49 +08:00
|
|
|
if(level != old_level)
|
2010-05-06 19:24:01 +08:00
|
|
|
edges++;
|
2016-09-12 15:19:49 +08:00
|
|
|
|
2010-05-06 19:24:01 +08:00
|
|
|
old_level = level;
|
|
|
|
}
|
2016-10-04 05:24:59 +08:00
|
|
|
if(edges > 20 ) { /* expected are 42 edges */
|
2010-05-06 19:24:01 +08:00
|
|
|
int t = timer->TC_CV;
|
2016-09-09 17:56:20 +08:00
|
|
|
int c = t / TAG_BIT_PERIOD;
|
2016-09-02 22:25:54 +08:00
|
|
|
|
2016-09-22 01:03:32 +08:00
|
|
|
ResetTimer(timer);
|
2016-08-26 23:17:40 +08:00
|
|
|
legic_prng_forward(c);
|
2010-05-06 19:24:01 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
2016-09-02 22:25:54 +08:00
|
|
|
|
2016-09-22 01:03:32 +08:00
|
|
|
ResetTimer(timer);
|
2010-05-06 19:24:01 +08:00
|
|
|
return -1;
|
|
|
|
}
|
2010-02-05 16:18:02 +08:00
|
|
|
|
2016-09-29 23:43:39 +08:00
|
|
|
int LegicRfReader(uint16_t offset, uint16_t len, uint8_t iv) {
|
2016-07-29 03:41:44 +08:00
|
|
|
|
2016-09-29 23:43:39 +08:00
|
|
|
len &= 0x3FF;
|
|
|
|
|
|
|
|
uint16_t i = 0;
|
2016-09-29 18:23:09 +08:00
|
|
|
uint8_t isOK = 1;
|
|
|
|
legic_card_select_t card;
|
|
|
|
|
2010-02-05 16:18:02 +08:00
|
|
|
LegicCommonInit();
|
2016-09-26 18:26:37 +08:00
|
|
|
|
2016-09-29 23:43:39 +08:00
|
|
|
if ( legic_select_card_iv(&card, iv) ) {
|
2016-09-29 18:23:09 +08:00
|
|
|
isOK = 0;
|
|
|
|
goto OUT;
|
|
|
|
}
|
2016-09-29 20:46:12 +08:00
|
|
|
|
2016-09-02 22:25:54 +08:00
|
|
|
switch_off_tag_rwd();
|
2016-09-29 20:46:12 +08:00
|
|
|
|
2016-09-29 23:43:39 +08:00
|
|
|
if (len + offset >= card.cardsize)
|
|
|
|
len = card.cardsize - offset;
|
2010-02-06 17:43:33 +08:00
|
|
|
|
2016-09-14 22:18:04 +08:00
|
|
|
setup_phase_reader(iv);
|
2016-09-29 03:37:08 +08:00
|
|
|
|
2010-05-06 19:24:01 +08:00
|
|
|
LED_B_ON();
|
2016-09-29 23:43:39 +08:00
|
|
|
while (i < len) {
|
|
|
|
int r = legic_read_byte(offset + i, card.cmdsize);
|
2016-09-09 17:56:20 +08:00
|
|
|
|
|
|
|
if (r == -1 || BUTTON_PRESS()) {
|
2016-09-29 23:43:39 +08:00
|
|
|
if ( MF_DBGLEVEL >= 2) DbpString("operation aborted");
|
2016-09-14 22:18:04 +08:00
|
|
|
isOK = 0;
|
|
|
|
goto OUT;
|
2010-02-06 17:43:33 +08:00
|
|
|
}
|
2016-09-29 23:43:39 +08:00
|
|
|
cardmem[i++] = r;
|
2010-05-06 19:24:01 +08:00
|
|
|
WDT_HIT();
|
2009-12-29 02:19:00 +08:00
|
|
|
}
|
2016-09-02 22:25:54 +08:00
|
|
|
|
2016-09-14 22:18:04 +08:00
|
|
|
OUT:
|
2016-09-26 18:26:37 +08:00
|
|
|
WDT_HIT();
|
2010-05-06 19:24:01 +08:00
|
|
|
switch_off_tag_rwd();
|
2016-09-02 22:25:54 +08:00
|
|
|
LEDsoff();
|
2016-09-14 22:18:04 +08:00
|
|
|
cmd_send(CMD_ACK,isOK,len,0,cardmem,len);
|
2010-05-06 19:24:01 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-08-26 23:17:40 +08:00
|
|
|
/*int _LegicRfWriter(int offset, int bytes, int addr_sz, uint8_t *BigBuf, int RoundBruteforceValue) {
|
2016-07-29 03:41:44 +08:00
|
|
|
int byte_index=0;
|
|
|
|
|
|
|
|
LED_B_ON();
|
2016-09-14 22:18:04 +08:00
|
|
|
setup_phase_reader(iv);
|
2016-07-29 03:41:44 +08:00
|
|
|
//legic_prng_forward(2);
|
|
|
|
while(byte_index < bytes) {
|
|
|
|
int r;
|
|
|
|
|
|
|
|
//check if the DCF should be changed
|
|
|
|
if ( (offset == 0x05) && (bytes == 0x02) ) {
|
|
|
|
//write DCF in reverse order (addr 0x06 before 0x05)
|
|
|
|
r = legic_write_byte(BigBuf[(0x06-byte_index)], (0x06-byte_index), addr_sz, RoundBruteforceValue);
|
|
|
|
//legic_prng_forward(1);
|
|
|
|
if(r == 0) {
|
|
|
|
byte_index++;
|
|
|
|
r = legic_write_byte(BigBuf[(0x06-byte_index)], (0x06-byte_index), addr_sz, RoundBruteforceValue);
|
|
|
|
}
|
|
|
|
//legic_prng_forward(1);
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
r = legic_write_byte(BigBuf[byte_index+offset], byte_index+offset, addr_sz, RoundBruteforceValue);
|
|
|
|
}
|
|
|
|
if((r != 0) || BUTTON_PRESS()) {
|
|
|
|
Dbprintf("operation aborted @ 0x%03.3x", byte_index);
|
|
|
|
switch_off_tag_rwd();
|
|
|
|
LED_B_OFF();
|
|
|
|
LED_C_OFF();
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
WDT_HIT();
|
|
|
|
byte_index++;
|
|
|
|
if(byte_index & 0x10) LED_C_ON(); else LED_C_OFF();
|
|
|
|
}
|
|
|
|
LED_B_OFF();
|
|
|
|
LED_C_OFF();
|
|
|
|
DbpString("write successful");
|
|
|
|
return 0;
|
|
|
|
}*/
|
|
|
|
|
2016-09-29 23:43:39 +08:00
|
|
|
void LegicRfWriter(uint16_t offset, uint16_t bytes, uint8_t iv) {
|
2015-01-16 18:00:17 +08:00
|
|
|
|
2016-09-29 23:43:39 +08:00
|
|
|
int byte_index = 0;
|
|
|
|
uint8_t isOK = 1;
|
|
|
|
legic_card_select_t card;
|
2010-05-06 19:24:01 +08:00
|
|
|
|
2016-09-29 23:43:39 +08:00
|
|
|
LegicCommonInit();
|
2016-09-02 22:25:54 +08:00
|
|
|
|
2016-09-29 23:43:39 +08:00
|
|
|
if ( legic_select_card_iv(&card, iv) ) {
|
|
|
|
isOK = 0;
|
|
|
|
goto OUT;
|
|
|
|
}
|
2016-09-02 22:25:54 +08:00
|
|
|
|
2010-02-05 16:18:02 +08:00
|
|
|
switch_off_tag_rwd();
|
2016-09-02 22:25:54 +08:00
|
|
|
|
2016-09-29 23:43:39 +08:00
|
|
|
switch(card.tagtype) {
|
2016-07-29 03:41:44 +08:00
|
|
|
case 0x0d:
|
|
|
|
if(offset+bytes > 22) {
|
2016-09-12 15:19:49 +08:00
|
|
|
Dbprintf("Error: can not write to 0x%03.3x on MIM22", offset + bytes);
|
2016-07-29 03:41:44 +08:00
|
|
|
return;
|
|
|
|
}
|
2016-09-12 15:19:49 +08:00
|
|
|
if ( MF_DBGLEVEL >= 2) Dbprintf("MIM22 card found, writing 0x%02.2x - 0x%02.2x ...", offset, offset + bytes);
|
2016-07-29 03:41:44 +08:00
|
|
|
break;
|
2010-05-06 19:24:01 +08:00
|
|
|
case 0x1d:
|
|
|
|
if(offset+bytes > 0x100) {
|
2016-09-12 15:19:49 +08:00
|
|
|
Dbprintf("Error: can not write to 0x%03.3x on MIM256", offset + bytes);
|
2010-05-06 19:24:01 +08:00
|
|
|
return;
|
|
|
|
}
|
2016-09-12 15:19:49 +08:00
|
|
|
if ( MF_DBGLEVEL >= 2) Dbprintf("MIM256 card found, writing 0x%02.2x - 0x%02.2x ...", offset, offset + bytes);
|
2010-05-06 19:24:01 +08:00
|
|
|
break;
|
|
|
|
case 0x3d:
|
|
|
|
if(offset+bytes > 0x400) {
|
2016-09-12 15:19:49 +08:00
|
|
|
Dbprintf("Error: can not write to 0x%03.3x on MIM1024", offset + bytes);
|
2010-05-06 19:24:01 +08:00
|
|
|
return;
|
|
|
|
}
|
2016-09-12 15:19:49 +08:00
|
|
|
if ( MF_DBGLEVEL >= 2) Dbprintf("MIM1024 card found, writing 0x%03.3x - 0x%03.3x ...", offset, offset + bytes);
|
2010-05-06 19:24:01 +08:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
LED_B_ON();
|
2016-09-14 22:18:04 +08:00
|
|
|
setup_phase_reader(iv);
|
2016-10-04 05:24:59 +08:00
|
|
|
|
2016-09-12 15:19:49 +08:00
|
|
|
int r = 0;
|
2010-05-06 19:24:01 +08:00
|
|
|
while(byte_index < bytes) {
|
2016-07-29 03:41:44 +08:00
|
|
|
|
|
|
|
//check if the DCF should be changed
|
|
|
|
if ( ((byte_index+offset) == 0x05) && (bytes >= 0x02) ) {
|
|
|
|
//write DCF in reverse order (addr 0x06 before 0x05)
|
2016-09-29 23:43:39 +08:00
|
|
|
r = legic_write_byte(cardmem[(0x06-byte_index)], (0x06-byte_index), card.addrsize);
|
2016-07-29 03:41:44 +08:00
|
|
|
|
2016-09-29 23:43:39 +08:00
|
|
|
// write second byte on success
|
2016-07-29 03:41:44 +08:00
|
|
|
if(r == 0) {
|
|
|
|
byte_index++;
|
2016-09-29 23:43:39 +08:00
|
|
|
r = legic_write_byte(cardmem[(0x06-byte_index)], (0x06-byte_index), card.addrsize);
|
2016-07-29 03:41:44 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else {
|
2016-09-29 23:43:39 +08:00
|
|
|
r = legic_write_byte(cardmem[byte_index+offset], byte_index+offset, card.addrsize);
|
2016-07-29 03:41:44 +08:00
|
|
|
}
|
2016-09-02 22:25:54 +08:00
|
|
|
|
2016-09-12 15:19:49 +08:00
|
|
|
if ((r != 0) || BUTTON_PRESS()) {
|
2010-05-06 19:24:01 +08:00
|
|
|
Dbprintf("operation aborted @ 0x%03.3x", byte_index);
|
2016-09-29 23:43:39 +08:00
|
|
|
isOK = 0;
|
|
|
|
goto OUT;
|
2010-05-06 19:24:01 +08:00
|
|
|
}
|
2016-07-29 03:41:44 +08:00
|
|
|
|
|
|
|
WDT_HIT();
|
|
|
|
byte_index++;
|
|
|
|
}
|
2016-09-29 23:43:39 +08:00
|
|
|
|
|
|
|
OUT:
|
|
|
|
cmd_send(CMD_ACK, isOK, 0,0,0,0);
|
|
|
|
switch_off_tag_rwd();
|
|
|
|
LEDsoff();
|
2016-07-29 03:41:44 +08:00
|
|
|
}
|
|
|
|
|
2016-09-29 23:43:39 +08:00
|
|
|
void LegicRfRawWriter(int address, int byte, uint8_t iv) {
|
2016-09-02 22:25:54 +08:00
|
|
|
|
|
|
|
int byte_index = 0, addr_sz = 0;
|
2016-07-29 03:41:44 +08:00
|
|
|
|
|
|
|
LegicCommonInit();
|
|
|
|
|
2016-09-02 22:25:54 +08:00
|
|
|
if ( MF_DBGLEVEL >= 2) DbpString("setting up legic card");
|
|
|
|
|
2016-09-14 22:18:04 +08:00
|
|
|
uint32_t tag_type = setup_phase_reader(iv);
|
2016-09-02 22:25:54 +08:00
|
|
|
|
2016-07-29 03:41:44 +08:00
|
|
|
switch_off_tag_rwd();
|
2016-09-02 22:25:54 +08:00
|
|
|
|
2016-07-29 03:41:44 +08:00
|
|
|
switch(tag_type) {
|
|
|
|
case 0x0d:
|
2016-08-26 23:17:40 +08:00
|
|
|
if(address > 22) {
|
|
|
|
Dbprintf("Error: can not write to 0x%03.3x on MIM22", address);
|
2016-07-29 03:41:44 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
addr_sz = 5;
|
2016-09-02 22:25:54 +08:00
|
|
|
if ( MF_DBGLEVEL >= 2) Dbprintf("MIM22 card found, writing at addr 0x%02.2x - value 0x%02.2x ...", address, byte);
|
2016-07-29 03:41:44 +08:00
|
|
|
break;
|
|
|
|
case 0x1d:
|
2016-08-26 23:17:40 +08:00
|
|
|
if(address > 0x100) {
|
|
|
|
Dbprintf("Error: can not write to 0x%03.3x on MIM256", address);
|
2016-07-29 03:41:44 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
addr_sz = 8;
|
2016-09-02 22:25:54 +08:00
|
|
|
if ( MF_DBGLEVEL >= 2) Dbprintf("MIM256 card found, writing at addr 0x%02.2x - value 0x%02.2x ...", address, byte);
|
2016-07-29 03:41:44 +08:00
|
|
|
break;
|
|
|
|
case 0x3d:
|
2016-08-26 23:17:40 +08:00
|
|
|
if(address > 0x400) {
|
|
|
|
Dbprintf("Error: can not write to 0x%03.3x on MIM1024", address);
|
2016-07-29 03:41:44 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
addr_sz = 10;
|
2016-09-02 22:25:54 +08:00
|
|
|
if ( MF_DBGLEVEL >= 2) Dbprintf("MIM1024 card found, writing at addr 0x%03.3x - value 0x%03.3x ...", address, byte);
|
2016-07-29 03:41:44 +08:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
Dbprintf("No or unknown card found, aborting");
|
|
|
|
return;
|
|
|
|
}
|
2016-09-02 22:25:54 +08:00
|
|
|
|
2016-08-26 23:17:40 +08:00
|
|
|
Dbprintf("integer value: %d address: %d addr_sz: %d", byte, address, addr_sz);
|
2016-07-29 03:41:44 +08:00
|
|
|
LED_B_ON();
|
2016-09-02 22:25:54 +08:00
|
|
|
|
2016-09-14 22:18:04 +08:00
|
|
|
setup_phase_reader(iv);
|
2016-09-12 15:19:49 +08:00
|
|
|
|
2016-08-26 23:17:40 +08:00
|
|
|
int r = legic_write_byte(byte, address, addr_sz);
|
2016-07-29 03:41:44 +08:00
|
|
|
|
|
|
|
if((r != 0) || BUTTON_PRESS()) {
|
|
|
|
Dbprintf("operation aborted @ 0x%03.3x (%1d)", byte_index, r);
|
|
|
|
switch_off_tag_rwd();
|
2016-09-02 22:25:54 +08:00
|
|
|
LEDsoff();
|
2016-07-29 03:41:44 +08:00
|
|
|
return;
|
2010-05-06 19:24:01 +08:00
|
|
|
}
|
|
|
|
|
2016-09-02 22:25:54 +08:00
|
|
|
LEDsoff();
|
|
|
|
if ( MF_DBGLEVEL >= 1) DbpString("write successful");
|
|
|
|
}
|
2010-05-06 19:24:01 +08:00
|
|
|
|
2016-09-29 23:43:39 +08:00
|
|
|
int legic_select_card_iv(legic_card_select_t *p_card, uint8_t iv){
|
2016-09-27 02:01:23 +08:00
|
|
|
|
2016-09-29 18:23:09 +08:00
|
|
|
if ( p_card == NULL ) return 1;
|
2016-09-27 02:01:23 +08:00
|
|
|
|
2016-09-29 23:43:39 +08:00
|
|
|
p_card->tagtype = setup_phase_reader(iv);
|
2016-09-29 18:23:09 +08:00
|
|
|
|
|
|
|
switch(p_card->tagtype) {
|
2016-09-27 02:01:23 +08:00
|
|
|
case 0x0d:
|
2016-09-29 18:23:09 +08:00
|
|
|
p_card->cmdsize = 6;
|
2016-09-29 23:43:39 +08:00
|
|
|
p_card->addrsize = 5;
|
2016-09-29 18:23:09 +08:00
|
|
|
p_card->cardsize = 22;
|
2016-09-27 02:01:23 +08:00
|
|
|
break;
|
|
|
|
case 0x1d:
|
2016-09-29 18:23:09 +08:00
|
|
|
p_card->cmdsize = 9;
|
2016-09-29 23:43:39 +08:00
|
|
|
p_card->addrsize = 8;
|
2016-09-29 18:23:09 +08:00
|
|
|
p_card->cardsize = 256;
|
2016-09-27 02:01:23 +08:00
|
|
|
break;
|
|
|
|
case 0x3d:
|
2016-09-29 18:23:09 +08:00
|
|
|
p_card->cmdsize = 11;
|
2016-09-29 23:43:39 +08:00
|
|
|
p_card->addrsize = 10;
|
2016-09-29 18:23:09 +08:00
|
|
|
p_card->cardsize = 1024;
|
2016-09-27 02:01:23 +08:00
|
|
|
break;
|
|
|
|
default:
|
2016-09-29 18:23:09 +08:00
|
|
|
p_card->cmdsize = 0;
|
2016-09-29 23:43:39 +08:00
|
|
|
p_card->addrsize = 0;
|
2016-09-29 18:23:09 +08:00
|
|
|
p_card->cardsize = 0;
|
|
|
|
return 2;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
2016-09-29 23:43:39 +08:00
|
|
|
int legic_select_card(legic_card_select_t *p_card){
|
|
|
|
return legic_select_card_iv(p_card, 0x01);
|
|
|
|
}
|
2016-09-29 18:23:09 +08:00
|
|
|
|
|
|
|
void LegicRfInfo(void){
|
|
|
|
|
|
|
|
uint8_t buf[sizeof(legic_card_select_t)] = {0x00};
|
|
|
|
legic_card_select_t *card = (legic_card_select_t*) buf;
|
|
|
|
|
|
|
|
LegicCommonInit();
|
2016-09-30 03:36:43 +08:00
|
|
|
|
2016-09-29 18:23:09 +08:00
|
|
|
if ( legic_select_card(card) ) {
|
|
|
|
cmd_send(CMD_ACK,0,0,0,0,0);
|
|
|
|
goto OUT;
|
2016-09-27 02:01:23 +08:00
|
|
|
}
|
|
|
|
|
2016-09-29 23:43:39 +08:00
|
|
|
// read UID bytes
|
2016-09-29 18:23:09 +08:00
|
|
|
for ( uint8_t i = 0; i < sizeof(card->uid); ++i) {
|
|
|
|
int r = legic_read_byte(i, card->cmdsize);
|
2016-09-27 02:01:23 +08:00
|
|
|
if ( r == -1 ) {
|
|
|
|
cmd_send(CMD_ACK,0,0,0,0,0);
|
|
|
|
goto OUT;
|
|
|
|
}
|
2016-09-29 18:23:09 +08:00
|
|
|
card->uid[i] = r & 0xFF;
|
2016-09-27 02:01:23 +08:00
|
|
|
}
|
|
|
|
|
2016-09-29 23:43:39 +08:00
|
|
|
cmd_send(CMD_ACK, 1, 0, 0, buf, sizeof(legic_card_select_t));
|
2016-09-29 18:23:09 +08:00
|
|
|
|
|
|
|
OUT:
|
2016-09-27 02:01:23 +08:00
|
|
|
switch_off_tag_rwd();
|
|
|
|
LEDsoff();
|
|
|
|
}
|
|
|
|
|
2016-09-02 22:25:54 +08:00
|
|
|
/* Handle (whether to respond) a frame in tag mode
|
|
|
|
* Only called when simulating a tag.
|
|
|
|
*/
|
2010-05-06 19:24:01 +08:00
|
|
|
static void frame_handle_tag(struct legic_frame const * const f)
|
|
|
|
{
|
2015-01-16 18:00:17 +08:00
|
|
|
uint8_t *BigBuf = BigBuf_get_addr();
|
|
|
|
|
2010-05-06 19:24:01 +08:00
|
|
|
/* First Part of Handshake (IV) */
|
|
|
|
if(f->bits == 7) {
|
2016-09-02 22:25:54 +08:00
|
|
|
|
2010-05-06 19:24:01 +08:00
|
|
|
LED_C_ON();
|
2016-09-02 22:25:54 +08:00
|
|
|
|
2016-09-09 17:56:20 +08:00
|
|
|
// Reset prng timer
|
2016-09-22 01:03:32 +08:00
|
|
|
ResetTimer(prng_timer);
|
2016-09-02 22:25:54 +08:00
|
|
|
|
2010-05-06 19:24:01 +08:00
|
|
|
legic_prng_init(f->data);
|
2016-09-09 17:56:20 +08:00
|
|
|
frame_send_tag(0x3d, 6, 1); /* 0x3d^0x26 = 0x1B */
|
2010-05-06 19:24:01 +08:00
|
|
|
legic_state = STATE_IV;
|
|
|
|
legic_read_count = 0;
|
|
|
|
legic_prng_bc = 0;
|
|
|
|
legic_prng_iv = f->data;
|
|
|
|
|
2016-09-12 15:19:49 +08:00
|
|
|
|
2016-09-22 01:03:32 +08:00
|
|
|
ResetTimer(timer);
|
|
|
|
WaitUS(280);
|
2010-05-06 19:24:01 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* 0x19==??? */
|
|
|
|
if(legic_state == STATE_IV) {
|
2016-08-26 23:17:40 +08:00
|
|
|
int local_key = get_key_stream(3, 6);
|
|
|
|
int xored = 0x39 ^ local_key;
|
|
|
|
if((f->bits == 6) && (f->data == xored)) {
|
2010-05-06 19:24:01 +08:00
|
|
|
legic_state = STATE_CON;
|
|
|
|
|
2016-09-22 01:03:32 +08:00
|
|
|
ResetTimer(timer);
|
|
|
|
WaitUS(200);
|
2010-05-06 19:24:01 +08:00
|
|
|
return;
|
2016-09-12 15:19:49 +08:00
|
|
|
|
|
|
|
} else {
|
2010-05-06 19:24:01 +08:00
|
|
|
legic_state = STATE_DISCON;
|
|
|
|
LED_C_OFF();
|
2016-08-26 23:17:40 +08:00
|
|
|
Dbprintf("iv: %02x frame: %02x key: %02x xored: %02x", legic_prng_iv, f->data, local_key, xored);
|
2010-05-06 19:24:01 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Read */
|
|
|
|
if(f->bits == 11) {
|
|
|
|
if(legic_state == STATE_CON) {
|
2016-08-26 23:17:40 +08:00
|
|
|
int key = get_key_stream(2, 11); //legic_phase_drift, 11);
|
2010-05-06 19:24:01 +08:00
|
|
|
int addr = f->data ^ key; addr = addr >> 1;
|
2015-01-16 18:00:17 +08:00
|
|
|
int data = BigBuf[addr];
|
2016-09-12 15:19:49 +08:00
|
|
|
int hash = legic4Crc(LEGIC_READ, addr, data, 11) << 8;
|
2015-01-16 18:00:17 +08:00
|
|
|
BigBuf[OFFSET_LOG+legic_read_count] = (uint8_t)addr;
|
2010-05-06 19:24:01 +08:00
|
|
|
legic_read_count++;
|
|
|
|
|
|
|
|
//Dbprintf("Data:%03.3x, key:%03.3x, addr: %03.3x, read_c:%u", f->data, key, addr, read_c);
|
|
|
|
legic_prng_forward(legic_reqresp_drift);
|
|
|
|
|
|
|
|
frame_send_tag(hash | data, 12, 1);
|
|
|
|
|
2016-09-22 01:03:32 +08:00
|
|
|
ResetTimer(timer);
|
2016-08-26 23:17:40 +08:00
|
|
|
legic_prng_forward(2);
|
2016-09-22 01:03:32 +08:00
|
|
|
WaitUS(180);
|
2010-05-06 19:24:01 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Write */
|
|
|
|
if(f->bits == 23) {
|
|
|
|
int key = get_key_stream(-1, 23); //legic_frame_drift, 23);
|
|
|
|
int addr = f->data ^ key; addr = addr >> 1; addr = addr & 0x3ff;
|
|
|
|
int data = f->data ^ key; data = data >> 11; data = data & 0xff;
|
|
|
|
|
|
|
|
/* write command */
|
|
|
|
legic_state = STATE_DISCON;
|
|
|
|
LED_C_OFF();
|
|
|
|
Dbprintf("write - addr: %x, data: %x", addr, data);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if(legic_state != STATE_DISCON) {
|
|
|
|
Dbprintf("Unexpected: sz:%u, Data:%03.3x, State:%u, Count:%u", f->bits, f->data, legic_state, legic_read_count);
|
|
|
|
int i;
|
|
|
|
Dbprintf("IV: %03.3x", legic_prng_iv);
|
|
|
|
for(i = 0; i<legic_read_count; i++) {
|
2015-01-16 18:00:17 +08:00
|
|
|
Dbprintf("Read Nb: %u, Addr: %u", i, BigBuf[OFFSET_LOG+i]);
|
2010-05-06 19:24:01 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
for(i = -1; i<legic_read_count; i++) {
|
|
|
|
uint32_t t;
|
2015-01-16 18:00:17 +08:00
|
|
|
t = BigBuf[OFFSET_LOG+256+i*4];
|
|
|
|
t |= BigBuf[OFFSET_LOG+256+i*4+1] << 8;
|
|
|
|
t |= BigBuf[OFFSET_LOG+256+i*4+2] <<16;
|
|
|
|
t |= BigBuf[OFFSET_LOG+256+i*4+3] <<24;
|
2010-05-06 19:24:01 +08:00
|
|
|
|
|
|
|
Dbprintf("Cycles: %u, Frame Length: %u, Time: %u",
|
2015-01-16 18:00:17 +08:00
|
|
|
BigBuf[OFFSET_LOG+128+i],
|
|
|
|
BigBuf[OFFSET_LOG+384+i],
|
2010-05-06 19:24:01 +08:00
|
|
|
t);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
legic_state = STATE_DISCON;
|
|
|
|
legic_read_count = 0;
|
|
|
|
SpinDelay(10);
|
|
|
|
LED_C_OFF();
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Read bit by bit untill full frame is received
|
|
|
|
* Call to process frame end answer
|
|
|
|
*/
|
2016-09-02 22:25:54 +08:00
|
|
|
static void emit(int bit) {
|
|
|
|
|
|
|
|
switch (bit) {
|
|
|
|
case 1:
|
|
|
|
frame_append_bit(¤t_frame, 1);
|
|
|
|
break;
|
|
|
|
case 0:
|
|
|
|
frame_append_bit(¤t_frame, 0);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
if(current_frame.bits <= 4) {
|
|
|
|
frame_clean(¤t_frame);
|
|
|
|
} else {
|
|
|
|
frame_handle_tag(¤t_frame);
|
|
|
|
frame_clean(¤t_frame);
|
|
|
|
}
|
|
|
|
WDT_HIT();
|
|
|
|
break;
|
|
|
|
}
|
2010-05-06 19:24:01 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void LegicRfSimulate(int phase, int frame, int reqresp)
|
|
|
|
{
|
|
|
|
/* ADC path high-frequency peak detector, FPGA in high-frequency simulator mode,
|
|
|
|
* modulation mode set to 212kHz subcarrier. We are getting the incoming raw
|
|
|
|
* envelope waveform on DIN and should send our response on DOUT.
|
|
|
|
*
|
|
|
|
* The LEGIC RF protocol is pulse-pause-encoding from reader to card, so we'll
|
|
|
|
* measure the time between two rising edges on DIN, and no encoding on the
|
|
|
|
* subcarrier from card to reader, so we'll just shift out our verbatim data
|
|
|
|
* on DOUT, 1 bit is 100us. The time from reader to card frame is still unclear,
|
|
|
|
* seems to be 300us-ish.
|
|
|
|
*/
|
|
|
|
|
2016-09-02 22:25:54 +08:00
|
|
|
legic_phase_drift = phase;
|
|
|
|
legic_frame_drift = frame;
|
|
|
|
legic_reqresp_drift = reqresp;
|
|
|
|
|
|
|
|
FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
|
|
|
|
SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
|
|
|
|
FpgaSetupSsc();
|
|
|
|
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_212K);
|
|
|
|
|
|
|
|
/* Bitbang the receiver */
|
|
|
|
AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
|
|
|
|
AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
|
|
|
|
|
2016-09-09 17:56:20 +08:00
|
|
|
//setup_timer();
|
2016-09-02 22:25:54 +08:00
|
|
|
crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
|
|
|
|
|
|
|
|
int old_level = 0;
|
|
|
|
int active = 0;
|
|
|
|
legic_state = STATE_DISCON;
|
|
|
|
|
|
|
|
LED_B_ON();
|
|
|
|
DbpString("Starting Legic emulator, press button to end");
|
2010-05-06 19:24:01 +08:00
|
|
|
|
2016-09-02 22:25:54 +08:00
|
|
|
while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
|
|
|
|
int level = !!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
|
|
|
|
int time = timer->TC_CV;
|
|
|
|
|
|
|
|
if(level != old_level) {
|
|
|
|
if(level == 1) {
|
|
|
|
timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
|
|
|
|
|
|
|
|
if (FUZZ_EQUAL(time, RWD_TIME_1, RWD_TIME_FUZZ)) {
|
|
|
|
/* 1 bit */
|
|
|
|
emit(1);
|
|
|
|
active = 1;
|
|
|
|
LED_A_ON();
|
|
|
|
} else if (FUZZ_EQUAL(time, RWD_TIME_0, RWD_TIME_FUZZ)) {
|
|
|
|
/* 0 bit */
|
|
|
|
emit(0);
|
|
|
|
active = 1;
|
|
|
|
LED_A_ON();
|
|
|
|
} else if (active) {
|
|
|
|
/* invalid */
|
|
|
|
emit(-1);
|
|
|
|
active = 0;
|
|
|
|
LED_A_OFF();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2010-05-06 19:24:01 +08:00
|
|
|
|
2016-09-02 22:25:54 +08:00
|
|
|
/* Frame end */
|
|
|
|
if(time >= (RWD_TIME_1+RWD_TIME_FUZZ) && active) {
|
|
|
|
emit(-1);
|
|
|
|
active = 0;
|
|
|
|
LED_A_OFF();
|
|
|
|
}
|
2010-02-06 17:43:33 +08:00
|
|
|
|
2016-09-02 22:25:54 +08:00
|
|
|
if(time >= (20*RWD_TIME_1) && (timer->TC_SR & AT91C_TC_CLKSTA)) {
|
|
|
|
timer->TC_CCR = AT91C_TC_CLKDIS;
|
|
|
|
}
|
|
|
|
|
|
|
|
old_level = level;
|
|
|
|
WDT_HIT();
|
|
|
|
}
|
|
|
|
if ( MF_DBGLEVEL >= 1) DbpString("Stopped");
|
|
|
|
LEDsoff();
|
|
|
|
}
|
2016-07-29 03:41:44 +08:00
|
|
|
|
|
|
|
//-----------------------------------------------------------------------------
|
|
|
|
// Code up a string of octets at layer 2 (including CRC, we don't generate
|
|
|
|
// that here) so that they can be transmitted to the reader. Doesn't transmit
|
|
|
|
// them yet, just leaves them ready to send in ToSend[].
|
|
|
|
//-----------------------------------------------------------------------------
|
|
|
|
// static void CodeLegicAsTag(const uint8_t *cmd, int len)
|
|
|
|
// {
|
|
|
|
// int i;
|
|
|
|
|
|
|
|
// ToSendReset();
|
|
|
|
|
|
|
|
// // Transmit a burst of ones, as the initial thing that lets the
|
|
|
|
// // reader get phase sync. This (TR1) must be > 80/fs, per spec,
|
|
|
|
// // but tag that I've tried (a Paypass) exceeds that by a fair bit,
|
|
|
|
// // so I will too.
|
|
|
|
// for(i = 0; i < 20; i++) {
|
|
|
|
// ToSendStuffBit(1);
|
|
|
|
// ToSendStuffBit(1);
|
|
|
|
// ToSendStuffBit(1);
|
|
|
|
// ToSendStuffBit(1);
|
|
|
|
// }
|
|
|
|
|
|
|
|
// // Send SOF.
|
|
|
|
// for(i = 0; i < 10; i++) {
|
|
|
|
// ToSendStuffBit(0);
|
|
|
|
// ToSendStuffBit(0);
|
|
|
|
// ToSendStuffBit(0);
|
|
|
|
// ToSendStuffBit(0);
|
|
|
|
// }
|
|
|
|
// for(i = 0; i < 2; i++) {
|
|
|
|
// ToSendStuffBit(1);
|
|
|
|
// ToSendStuffBit(1);
|
|
|
|
// ToSendStuffBit(1);
|
|
|
|
// ToSendStuffBit(1);
|
|
|
|
// }
|
|
|
|
|
|
|
|
// for(i = 0; i < len; i++) {
|
|
|
|
// int j;
|
|
|
|
// uint8_t b = cmd[i];
|
|
|
|
|
|
|
|
// // Start bit
|
|
|
|
// ToSendStuffBit(0);
|
|
|
|
// ToSendStuffBit(0);
|
|
|
|
// ToSendStuffBit(0);
|
|
|
|
// ToSendStuffBit(0);
|
|
|
|
|
|
|
|
// // Data bits
|
|
|
|
// for(j = 0; j < 8; j++) {
|
|
|
|
// if(b & 1) {
|
|
|
|
// ToSendStuffBit(1);
|
|
|
|
// ToSendStuffBit(1);
|
|
|
|
// ToSendStuffBit(1);
|
|
|
|
// ToSendStuffBit(1);
|
|
|
|
// } else {
|
|
|
|
// ToSendStuffBit(0);
|
|
|
|
// ToSendStuffBit(0);
|
|
|
|
// ToSendStuffBit(0);
|
|
|
|
// ToSendStuffBit(0);
|
|
|
|
// }
|
|
|
|
// b >>= 1;
|
|
|
|
// }
|
|
|
|
|
|
|
|
// // Stop bit
|
|
|
|
// ToSendStuffBit(1);
|
|
|
|
// ToSendStuffBit(1);
|
|
|
|
// ToSendStuffBit(1);
|
|
|
|
// ToSendStuffBit(1);
|
|
|
|
// }
|
|
|
|
|
|
|
|
// // Send EOF.
|
|
|
|
// for(i = 0; i < 10; i++) {
|
|
|
|
// ToSendStuffBit(0);
|
|
|
|
// ToSendStuffBit(0);
|
|
|
|
// ToSendStuffBit(0);
|
|
|
|
// ToSendStuffBit(0);
|
|
|
|
// }
|
|
|
|
// for(i = 0; i < 2; i++) {
|
|
|
|
// ToSendStuffBit(1);
|
|
|
|
// ToSendStuffBit(1);
|
|
|
|
// ToSendStuffBit(1);
|
|
|
|
// ToSendStuffBit(1);
|
|
|
|
// }
|
|
|
|
|
|
|
|
// // Convert from last byte pos to length
|
|
|
|
// ToSendMax++;
|
|
|
|
// }
|
|
|
|
|
|
|
|
//-----------------------------------------------------------------------------
|
|
|
|
// The software UART that receives commands from the reader, and its state
|
|
|
|
// variables.
|
|
|
|
//-----------------------------------------------------------------------------
|
2016-09-27 02:21:31 +08:00
|
|
|
/*
|
2016-07-29 03:41:44 +08:00
|
|
|
static struct {
|
|
|
|
enum {
|
|
|
|
STATE_UNSYNCD,
|
|
|
|
STATE_GOT_FALLING_EDGE_OF_SOF,
|
|
|
|
STATE_AWAITING_START_BIT,
|
|
|
|
STATE_RECEIVING_DATA
|
|
|
|
} state;
|
|
|
|
uint16_t shiftReg;
|
|
|
|
int bitCnt;
|
|
|
|
int byteCnt;
|
|
|
|
int byteCntMax;
|
|
|
|
int posCnt;
|
|
|
|
uint8_t *output;
|
|
|
|
} Uart;
|
2016-09-27 02:21:31 +08:00
|
|
|
*/
|
2016-07-29 03:41:44 +08:00
|
|
|
/* Receive & handle a bit coming from the reader.
|
|
|
|
*
|
|
|
|
* This function is called 4 times per bit (every 2 subcarrier cycles).
|
|
|
|
* Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
|
|
|
|
*
|
|
|
|
* LED handling:
|
|
|
|
* LED A -> ON once we have received the SOF and are expecting the rest.
|
|
|
|
* LED A -> OFF once we have received EOF or are in error state or unsynced
|
|
|
|
*
|
|
|
|
* Returns: true if we received a EOF
|
|
|
|
* false if we are still waiting for some more
|
|
|
|
*/
|
|
|
|
// static RAMFUNC int HandleLegicUartBit(uint8_t bit)
|
|
|
|
// {
|
|
|
|
// switch(Uart.state) {
|
|
|
|
// case STATE_UNSYNCD:
|
|
|
|
// if(!bit) {
|
|
|
|
// // we went low, so this could be the beginning of an SOF
|
|
|
|
// Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
|
|
|
|
// Uart.posCnt = 0;
|
|
|
|
// Uart.bitCnt = 0;
|
|
|
|
// }
|
|
|
|
// break;
|
|
|
|
|
|
|
|
// case STATE_GOT_FALLING_EDGE_OF_SOF:
|
|
|
|
// Uart.posCnt++;
|
|
|
|
// if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
|
|
|
|
// if(bit) {
|
|
|
|
// if(Uart.bitCnt > 9) {
|
|
|
|
// // we've seen enough consecutive
|
|
|
|
// // zeros that it's a valid SOF
|
|
|
|
// Uart.posCnt = 0;
|
|
|
|
// Uart.byteCnt = 0;
|
|
|
|
// Uart.state = STATE_AWAITING_START_BIT;
|
|
|
|
// LED_A_ON(); // Indicate we got a valid SOF
|
|
|
|
// } else {
|
|
|
|
// // didn't stay down long enough
|
|
|
|
// // before going high, error
|
|
|
|
// Uart.state = STATE_UNSYNCD;
|
|
|
|
// }
|
|
|
|
// } else {
|
|
|
|
// // do nothing, keep waiting
|
|
|
|
// }
|
|
|
|
// Uart.bitCnt++;
|
|
|
|
// }
|
|
|
|
// if(Uart.posCnt >= 4) Uart.posCnt = 0;
|
|
|
|
// if(Uart.bitCnt > 12) {
|
|
|
|
// // Give up if we see too many zeros without
|
|
|
|
// // a one, too.
|
|
|
|
// LED_A_OFF();
|
|
|
|
// Uart.state = STATE_UNSYNCD;
|
|
|
|
// }
|
|
|
|
// break;
|
|
|
|
|
|
|
|
// case STATE_AWAITING_START_BIT:
|
|
|
|
// Uart.posCnt++;
|
|
|
|
// if(bit) {
|
|
|
|
// if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
|
|
|
|
// // stayed high for too long between
|
|
|
|
// // characters, error
|
|
|
|
// Uart.state = STATE_UNSYNCD;
|
|
|
|
// }
|
|
|
|
// } else {
|
|
|
|
// // falling edge, this starts the data byte
|
|
|
|
// Uart.posCnt = 0;
|
|
|
|
// Uart.bitCnt = 0;
|
|
|
|
// Uart.shiftReg = 0;
|
|
|
|
// Uart.state = STATE_RECEIVING_DATA;
|
|
|
|
// }
|
|
|
|
// break;
|
|
|
|
|
|
|
|
// case STATE_RECEIVING_DATA:
|
|
|
|
// Uart.posCnt++;
|
|
|
|
// if(Uart.posCnt == 2) {
|
|
|
|
// // time to sample a bit
|
|
|
|
// Uart.shiftReg >>= 1;
|
|
|
|
// if(bit) {
|
|
|
|
// Uart.shiftReg |= 0x200;
|
|
|
|
// }
|
|
|
|
// Uart.bitCnt++;
|
|
|
|
// }
|
|
|
|
// if(Uart.posCnt >= 4) {
|
|
|
|
// Uart.posCnt = 0;
|
|
|
|
// }
|
|
|
|
// if(Uart.bitCnt == 10) {
|
|
|
|
// if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
|
|
|
|
// {
|
|
|
|
// // this is a data byte, with correct
|
|
|
|
// // start and stop bits
|
|
|
|
// Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
|
|
|
|
// Uart.byteCnt++;
|
|
|
|
|
|
|
|
// if(Uart.byteCnt >= Uart.byteCntMax) {
|
|
|
|
// // Buffer overflowed, give up
|
|
|
|
// LED_A_OFF();
|
|
|
|
// Uart.state = STATE_UNSYNCD;
|
|
|
|
// } else {
|
|
|
|
// // so get the next byte now
|
|
|
|
// Uart.posCnt = 0;
|
|
|
|
// Uart.state = STATE_AWAITING_START_BIT;
|
|
|
|
// }
|
|
|
|
// } else if (Uart.shiftReg == 0x000) {
|
|
|
|
// // this is an EOF byte
|
|
|
|
// LED_A_OFF(); // Finished receiving
|
|
|
|
// Uart.state = STATE_UNSYNCD;
|
|
|
|
// if (Uart.byteCnt != 0) {
|
|
|
|
// return TRUE;
|
|
|
|
// }
|
|
|
|
// } else {
|
|
|
|
// // this is an error
|
|
|
|
// LED_A_OFF();
|
|
|
|
// Uart.state = STATE_UNSYNCD;
|
|
|
|
// }
|
|
|
|
// }
|
|
|
|
// break;
|
|
|
|
|
|
|
|
// default:
|
|
|
|
// LED_A_OFF();
|
|
|
|
// Uart.state = STATE_UNSYNCD;
|
|
|
|
// break;
|
|
|
|
// }
|
|
|
|
|
|
|
|
// return FALSE;
|
|
|
|
// }
|
2016-09-27 02:21:31 +08:00
|
|
|
/*
|
2016-07-29 03:41:44 +08:00
|
|
|
|
2016-09-03 18:18:02 +08:00
|
|
|
static void UartReset() {
|
|
|
|
Uart.byteCntMax = 3;
|
2016-07-29 03:41:44 +08:00
|
|
|
Uart.state = STATE_UNSYNCD;
|
|
|
|
Uart.byteCnt = 0;
|
|
|
|
Uart.bitCnt = 0;
|
|
|
|
Uart.posCnt = 0;
|
2016-09-03 18:18:02 +08:00
|
|
|
memset(Uart.output, 0x00, 3);
|
2016-07-29 03:41:44 +08:00
|
|
|
}
|
2016-09-27 02:21:31 +08:00
|
|
|
*/
|
2016-09-03 18:18:02 +08:00
|
|
|
// static void UartInit(uint8_t *data) {
|
2016-07-29 03:41:44 +08:00
|
|
|
// Uart.output = data;
|
|
|
|
// UartReset();
|
|
|
|
// }
|
|
|
|
|
|
|
|
//=============================================================================
|
|
|
|
// An LEGIC reader. We take layer two commands, code them
|
|
|
|
// appropriately, and then send them to the tag. We then listen for the
|
|
|
|
// tag's response, which we leave in the buffer to be demodulated on the
|
|
|
|
// PC side.
|
|
|
|
//=============================================================================
|
2016-09-27 02:21:31 +08:00
|
|
|
/*
|
2016-07-29 03:41:44 +08:00
|
|
|
static struct {
|
|
|
|
enum {
|
|
|
|
DEMOD_UNSYNCD,
|
|
|
|
DEMOD_PHASE_REF_TRAINING,
|
|
|
|
DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
|
|
|
|
DEMOD_GOT_FALLING_EDGE_OF_SOF,
|
|
|
|
DEMOD_AWAITING_START_BIT,
|
|
|
|
DEMOD_RECEIVING_DATA
|
|
|
|
} state;
|
|
|
|
int bitCount;
|
|
|
|
int posCount;
|
|
|
|
int thisBit;
|
|
|
|
uint16_t shiftReg;
|
|
|
|
uint8_t *output;
|
|
|
|
int len;
|
|
|
|
int sumI;
|
|
|
|
int sumQ;
|
|
|
|
} Demod;
|
2016-09-27 02:21:31 +08:00
|
|
|
*/
|
2016-07-29 03:41:44 +08:00
|
|
|
/*
|
|
|
|
* Handles reception of a bit from the tag
|
|
|
|
*
|
|
|
|
* This function is called 2 times per bit (every 4 subcarrier cycles).
|
|
|
|
* Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
|
|
|
|
*
|
|
|
|
* LED handling:
|
|
|
|
* LED C -> ON once we have received the SOF and are expecting the rest.
|
|
|
|
* LED C -> OFF once we have received EOF or are unsynced
|
|
|
|
*
|
|
|
|
* Returns: true if we received a EOF
|
|
|
|
* false if we are still waiting for some more
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
|
2016-09-27 02:21:31 +08:00
|
|
|
/*
|
2016-07-29 03:41:44 +08:00
|
|
|
static RAMFUNC int HandleLegicSamplesDemod(int ci, int cq)
|
|
|
|
{
|
|
|
|
int v = 0;
|
|
|
|
int ai = ABS(ci);
|
|
|
|
int aq = ABS(cq);
|
|
|
|
int halfci = (ai >> 1);
|
|
|
|
int halfcq = (aq >> 1);
|
|
|
|
|
|
|
|
switch(Demod.state) {
|
|
|
|
case DEMOD_UNSYNCD:
|
|
|
|
|
|
|
|
CHECK_FOR_SUBCARRIER()
|
|
|
|
|
|
|
|
if(v > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected
|
|
|
|
Demod.state = DEMOD_PHASE_REF_TRAINING;
|
|
|
|
Demod.sumI = ci;
|
|
|
|
Demod.sumQ = cq;
|
|
|
|
Demod.posCount = 1;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DEMOD_PHASE_REF_TRAINING:
|
|
|
|
if(Demod.posCount < 8) {
|
|
|
|
|
|
|
|
CHECK_FOR_SUBCARRIER()
|
|
|
|
|
|
|
|
if (v > SUBCARRIER_DETECT_THRESHOLD) {
|
|
|
|
// set the reference phase (will code a logic '1') by averaging over 32 1/fs.
|
|
|
|
// note: synchronization time > 80 1/fs
|
|
|
|
Demod.sumI += ci;
|
|
|
|
Demod.sumQ += cq;
|
|
|
|
++Demod.posCount;
|
|
|
|
} else {
|
|
|
|
// subcarrier lost
|
|
|
|
Demod.state = DEMOD_UNSYNCD;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
|
|
|
|
|
|
|
|
MAKE_SOFT_DECISION()
|
|
|
|
|
|
|
|
//Dbprintf("ICE: %d %d %d %d %d", v, Demod.sumI, Demod.sumQ, ci, cq );
|
|
|
|
// logic '0' detected
|
|
|
|
if (v <= 0) {
|
|
|
|
|
|
|
|
Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
|
|
|
|
|
|
|
|
// start of SOF sequence
|
|
|
|
Demod.posCount = 0;
|
|
|
|
} else {
|
|
|
|
// maximum length of TR1 = 200 1/fs
|
|
|
|
if(Demod.posCount > 25*2) Demod.state = DEMOD_UNSYNCD;
|
|
|
|
}
|
|
|
|
++Demod.posCount;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DEMOD_GOT_FALLING_EDGE_OF_SOF:
|
|
|
|
++Demod.posCount;
|
|
|
|
|
|
|
|
MAKE_SOFT_DECISION()
|
|
|
|
|
|
|
|
if(v > 0) {
|
|
|
|
// low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
|
|
|
|
if(Demod.posCount < 10*2) {
|
|
|
|
Demod.state = DEMOD_UNSYNCD;
|
|
|
|
} else {
|
|
|
|
LED_C_ON(); // Got SOF
|
|
|
|
Demod.state = DEMOD_AWAITING_START_BIT;
|
|
|
|
Demod.posCount = 0;
|
|
|
|
Demod.len = 0;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
// low phase of SOF too long (> 12 etu)
|
|
|
|
if(Demod.posCount > 13*2) {
|
|
|
|
Demod.state = DEMOD_UNSYNCD;
|
|
|
|
LED_C_OFF();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DEMOD_AWAITING_START_BIT:
|
|
|
|
++Demod.posCount;
|
|
|
|
|
|
|
|
MAKE_SOFT_DECISION()
|
|
|
|
|
|
|
|
if(v > 0) {
|
|
|
|
// max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
|
|
|
|
if(Demod.posCount > 3*2) {
|
|
|
|
Demod.state = DEMOD_UNSYNCD;
|
|
|
|
LED_C_OFF();
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
// start bit detected
|
|
|
|
Demod.bitCount = 0;
|
|
|
|
Demod.posCount = 1; // this was the first half
|
|
|
|
Demod.thisBit = v;
|
|
|
|
Demod.shiftReg = 0;
|
|
|
|
Demod.state = DEMOD_RECEIVING_DATA;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DEMOD_RECEIVING_DATA:
|
|
|
|
|
|
|
|
MAKE_SOFT_DECISION()
|
|
|
|
|
|
|
|
if(Demod.posCount == 0) {
|
|
|
|
// first half of bit
|
|
|
|
Demod.thisBit = v;
|
|
|
|
Demod.posCount = 1;
|
|
|
|
} else {
|
|
|
|
// second half of bit
|
|
|
|
Demod.thisBit += v;
|
|
|
|
Demod.shiftReg >>= 1;
|
|
|
|
// logic '1'
|
|
|
|
if(Demod.thisBit > 0)
|
|
|
|
Demod.shiftReg |= 0x200;
|
|
|
|
|
|
|
|
++Demod.bitCount;
|
|
|
|
|
|
|
|
if(Demod.bitCount == 10) {
|
|
|
|
|
|
|
|
uint16_t s = Demod.shiftReg;
|
|
|
|
|
|
|
|
if((s & 0x200) && !(s & 0x001)) {
|
|
|
|
// stop bit == '1', start bit == '0'
|
|
|
|
uint8_t b = (s >> 1);
|
|
|
|
Demod.output[Demod.len] = b;
|
|
|
|
++Demod.len;
|
|
|
|
Demod.state = DEMOD_AWAITING_START_BIT;
|
|
|
|
} else {
|
|
|
|
Demod.state = DEMOD_UNSYNCD;
|
|
|
|
LED_C_OFF();
|
|
|
|
|
|
|
|
if(s == 0x000) {
|
|
|
|
// This is EOF (start, stop and all data bits == '0'
|
|
|
|
return TRUE;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
Demod.posCount = 0;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
Demod.state = DEMOD_UNSYNCD;
|
|
|
|
LED_C_OFF();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return FALSE;
|
|
|
|
}
|
2016-09-27 02:21:31 +08:00
|
|
|
*/
|
|
|
|
/*
|
2016-07-29 03:41:44 +08:00
|
|
|
// Clear out the state of the "UART" that receives from the tag.
|
|
|
|
static void DemodReset() {
|
|
|
|
Demod.len = 0;
|
|
|
|
Demod.state = DEMOD_UNSYNCD;
|
|
|
|
Demod.posCount = 0;
|
|
|
|
Demod.sumI = 0;
|
|
|
|
Demod.sumQ = 0;
|
|
|
|
Demod.bitCount = 0;
|
|
|
|
Demod.thisBit = 0;
|
|
|
|
Demod.shiftReg = 0;
|
2016-09-03 18:18:02 +08:00
|
|
|
memset(Demod.output, 0x00, 3);
|
2016-07-29 03:41:44 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void DemodInit(uint8_t *data) {
|
|
|
|
Demod.output = data;
|
|
|
|
DemodReset();
|
|
|
|
}
|
2016-09-27 02:21:31 +08:00
|
|
|
*/
|
2016-07-29 03:41:44 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Demodulate the samples we received from the tag, also log to tracebuffer
|
|
|
|
* quiet: set to 'TRUE' to disable debug output
|
|
|
|
*/
|
2016-09-27 02:21:31 +08:00
|
|
|
|
|
|
|
/*
|
2016-07-29 03:41:44 +08:00
|
|
|
#define LEGIC_DMA_BUFFER_SIZE 256
|
2016-09-27 02:21:31 +08:00
|
|
|
|
|
|
|
static void GetSamplesForLegicDemod(int n, bool quiet)
|
2016-07-29 03:41:44 +08:00
|
|
|
{
|
|
|
|
int max = 0;
|
|
|
|
bool gotFrame = FALSE;
|
|
|
|
int lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
|
|
|
|
int ci, cq, samples = 0;
|
|
|
|
|
|
|
|
BigBuf_free();
|
|
|
|
|
|
|
|
// And put the FPGA in the appropriate mode
|
|
|
|
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_QUARTER_FREQ);
|
|
|
|
|
|
|
|
// The response (tag -> reader) that we're receiving.
|
|
|
|
// Set up the demodulator for tag -> reader responses.
|
|
|
|
DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
|
|
|
|
|
|
|
|
// The DMA buffer, used to stream samples from the FPGA
|
|
|
|
int8_t *dmaBuf = (int8_t*) BigBuf_malloc(LEGIC_DMA_BUFFER_SIZE);
|
|
|
|
int8_t *upTo = dmaBuf;
|
|
|
|
|
|
|
|
// Setup and start DMA.
|
|
|
|
if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, LEGIC_DMA_BUFFER_SIZE) ){
|
|
|
|
if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Signal field is ON with the appropriate LED:
|
|
|
|
LED_D_ON();
|
|
|
|
for(;;) {
|
|
|
|
int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;
|
|
|
|
if(behindBy > max) max = behindBy;
|
|
|
|
|
|
|
|
while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (LEGIC_DMA_BUFFER_SIZE-1)) > 2) {
|
|
|
|
ci = upTo[0];
|
|
|
|
cq = upTo[1];
|
|
|
|
upTo += 2;
|
|
|
|
if(upTo >= dmaBuf + LEGIC_DMA_BUFFER_SIZE) {
|
|
|
|
upTo = dmaBuf;
|
|
|
|
AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
|
|
|
|
AT91C_BASE_PDC_SSC->PDC_RNCR = LEGIC_DMA_BUFFER_SIZE;
|
|
|
|
}
|
|
|
|
lastRxCounter -= 2;
|
|
|
|
if(lastRxCounter <= 0)
|
|
|
|
lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
|
|
|
|
|
|
|
|
samples += 2;
|
|
|
|
|
|
|
|
gotFrame = HandleLegicSamplesDemod(ci , cq );
|
|
|
|
if ( gotFrame )
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if(samples > n || gotFrame)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
FpgaDisableSscDma();
|
|
|
|
|
|
|
|
if (!quiet && Demod.len == 0) {
|
|
|
|
Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d",
|
|
|
|
max,
|
|
|
|
samples,
|
|
|
|
gotFrame,
|
|
|
|
Demod.len,
|
|
|
|
Demod.sumI,
|
|
|
|
Demod.sumQ
|
|
|
|
);
|
|
|
|
}
|
|
|
|
|
|
|
|
//Tracing
|
|
|
|
if (Demod.len > 0) {
|
|
|
|
uint8_t parity[MAX_PARITY_SIZE] = {0x00};
|
|
|
|
LogTrace(Demod.output, Demod.len, 0, 0, parity, FALSE);
|
|
|
|
}
|
|
|
|
}
|
2016-09-27 02:21:31 +08:00
|
|
|
|
|
|
|
*/
|
|
|
|
|
2016-07-29 03:41:44 +08:00
|
|
|
//-----------------------------------------------------------------------------
|
|
|
|
// Transmit the command (to the tag) that was placed in ToSend[].
|
|
|
|
//-----------------------------------------------------------------------------
|
2016-09-27 02:21:31 +08:00
|
|
|
/*
|
2016-07-29 03:41:44 +08:00
|
|
|
static void TransmitForLegic(void)
|
|
|
|
{
|
|
|
|
int c;
|
|
|
|
|
|
|
|
FpgaSetupSsc();
|
|
|
|
|
|
|
|
while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY))
|
|
|
|
AT91C_BASE_SSC->SSC_THR = 0xff;
|
|
|
|
|
|
|
|
// Signal field is ON with the appropriate Red LED
|
|
|
|
LED_D_ON();
|
|
|
|
|
|
|
|
// Signal we are transmitting with the Green LED
|
|
|
|
LED_B_ON();
|
|
|
|
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
|
|
|
|
|
|
|
|
for(c = 0; c < 10;) {
|
|
|
|
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
|
|
|
|
AT91C_BASE_SSC->SSC_THR = 0xff;
|
|
|
|
c++;
|
|
|
|
}
|
|
|
|
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
|
|
|
|
volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
|
|
|
|
(void)r;
|
|
|
|
}
|
|
|
|
WDT_HIT();
|
|
|
|
}
|
|
|
|
|
|
|
|
c = 0;
|
|
|
|
for(;;) {
|
|
|
|
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
|
|
|
|
AT91C_BASE_SSC->SSC_THR = ToSend[c];
|
|
|
|
legic_prng_forward(1); // forward the lfsr
|
|
|
|
c++;
|
|
|
|
if(c >= ToSendMax) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
|
|
|
|
volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
|
|
|
|
(void)r;
|
|
|
|
}
|
|
|
|
WDT_HIT();
|
|
|
|
}
|
|
|
|
LED_B_OFF();
|
|
|
|
}
|
2016-09-27 02:21:31 +08:00
|
|
|
*/
|
2016-07-29 03:41:44 +08:00
|
|
|
|
|
|
|
//-----------------------------------------------------------------------------
|
|
|
|
// Code a layer 2 command (string of octets, including CRC) into ToSend[],
|
|
|
|
// so that it is ready to transmit to the tag using TransmitForLegic().
|
|
|
|
//-----------------------------------------------------------------------------
|
2016-09-27 02:21:31 +08:00
|
|
|
/*
|
2016-08-02 22:04:03 +08:00
|
|
|
static void CodeLegicBitsAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
|
2016-07-29 03:41:44 +08:00
|
|
|
{
|
|
|
|
int i, j;
|
|
|
|
uint8_t b;
|
|
|
|
|
|
|
|
ToSendReset();
|
|
|
|
|
|
|
|
// Send SOF
|
2016-08-02 22:04:03 +08:00
|
|
|
for(i = 0; i < 7; i++)
|
2016-07-29 03:41:44 +08:00
|
|
|
ToSendStuffBit(1);
|
|
|
|
|
2016-08-02 22:04:03 +08:00
|
|
|
|
|
|
|
for(i = 0; i < cmdlen; i++) {
|
2016-07-29 03:41:44 +08:00
|
|
|
// Start bit
|
|
|
|
ToSendStuffBit(0);
|
|
|
|
|
|
|
|
// Data bits
|
|
|
|
b = cmd[i];
|
2016-08-02 22:04:03 +08:00
|
|
|
for(j = 0; j < bits; j++) {
|
2016-07-29 03:41:44 +08:00
|
|
|
if(b & 1) {
|
|
|
|
ToSendStuffBit(1);
|
|
|
|
} else {
|
|
|
|
ToSendStuffBit(0);
|
|
|
|
}
|
|
|
|
b >>= 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Convert from last character reference to length
|
|
|
|
++ToSendMax;
|
|
|
|
}
|
2016-09-27 02:21:31 +08:00
|
|
|
*/
|
2016-07-29 03:41:44 +08:00
|
|
|
/**
|
|
|
|
Convenience function to encode, transmit and trace Legic comms
|
|
|
|
**/
|
2016-09-27 02:21:31 +08:00
|
|
|
/*
|
|
|
|
static void CodeAndTransmitLegicAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
|
2016-07-29 03:41:44 +08:00
|
|
|
{
|
2016-08-02 22:04:03 +08:00
|
|
|
CodeLegicBitsAsReader(cmd, cmdlen, bits);
|
2016-07-29 03:41:44 +08:00
|
|
|
TransmitForLegic();
|
|
|
|
if (tracing) {
|
|
|
|
uint8_t parity[1] = {0x00};
|
2016-08-03 06:25:53 +08:00
|
|
|
LogTrace(cmd, cmdlen, 0, 0, parity, TRUE);
|
2016-07-29 03:41:44 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-09-27 02:21:31 +08:00
|
|
|
*/
|
2016-07-29 03:41:44 +08:00
|
|
|
// Set up LEGIC communication
|
2016-09-27 02:21:31 +08:00
|
|
|
/*
|
2016-07-29 03:41:44 +08:00
|
|
|
void ice_legic_setup() {
|
|
|
|
|
|
|
|
// standard things.
|
|
|
|
FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
|
|
|
|
BigBuf_free(); BigBuf_Clear_ext(false);
|
|
|
|
clear_trace();
|
|
|
|
set_tracing(TRUE);
|
|
|
|
DemodReset();
|
|
|
|
UartReset();
|
|
|
|
|
|
|
|
// Set up the synchronous serial port
|
|
|
|
FpgaSetupSsc();
|
|
|
|
|
|
|
|
// connect Demodulated Signal to ADC:
|
|
|
|
SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
|
|
|
|
|
|
|
|
// Signal field is on with the appropriate LED
|
|
|
|
LED_D_ON();
|
|
|
|
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
|
2016-09-03 18:18:02 +08:00
|
|
|
SpinDelay(20);
|
2016-07-29 03:41:44 +08:00
|
|
|
// Start the timer
|
|
|
|
//StartCountSspClk();
|
|
|
|
|
|
|
|
// initalize CRC
|
|
|
|
crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
|
|
|
|
|
|
|
|
// initalize prng
|
|
|
|
legic_prng_init(0);
|
2016-09-27 02:21:31 +08:00
|
|
|
}
|
|
|
|
*/
|