RfidResearchGroup/proxmark3
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4033 commits 3 branches 15 tags 87 MiB
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1213 commits

Author SHA1 Message Date
Andreas Dröscher
0d0b651246 change: re-added trace log 2018-08-12 12:51:45 +02:00
Andreas Dröscher
ff5b046903 change: re-added status LEDs 
- LED_A: FPGA and 13.56MHz carrier is active
- LED_B: Reading Byte
- LED_C: Writing Byte
 2018-08-12 12:41:45 +02:00
Andreas Dröscher
e052fbc433 change: re-added legic write support 2018-08-12 12:41:45 +02:00
Andreas Dröscher
9d330dde87 fix: 32bit tick timer based on TC0 and TC1 
TC1 counts the number of TC0 overflows (carry bits).
In random conditions TC1 would return or stay at zero,
instead of counting up. This due to the behavior of the
reset signal.

SAM7S Series Datasheet, 33.5.6 Trigger:
Regardless of the trigger used, it will be taken into account
at the following active edge of the selected clock. This means
that the counter value can be read differently from zero just
after a trigger, especially when a low frequency signal is
selected as the clock.

The new code first prepares TC1 and asserts TC1 trigger and
then prepares TC0 and asserts TC0 trigger. The TC0 start-up
will reset TC1.
 2018-08-12 12:41:11 +02:00
Andreas Dröscher
c06f0af7f3 change: switched from timestamps (us) to ticks 
GetCountUS() has a jitter of +/- 7us this is not precise
enough to keep the PRNG in sync. 1.5 * GET_TICKS on the
other hand is spot on.
 2018-08-12 09:59:48 +02:00
Andreas Dröscher
e0adc976e0 change: added rx/tx coordination timestamp 2018-08-12 09:59:48 +02:00
Andreas Dröscher
7244f5825d change: legic reader tx back to bigbang 
I've tried to modulate the Legic specific pause-puls using ssc and the default
ssc clock of 105.4 kHz (bit periode of 9.4us) - previous commit. However,
the timing was not precise enough. By increasing the ssc clock this could
be circumvented, but the adventage over bitbang would be little.
 2018-08-12 09:59:48 +02:00
Andreas Dröscher
3029223158 change: legic reader now uses xcorrelation and ssc based io 
- Even tough legic tags transmit just AM using xcorrelation
   results in a significantly better signal quality.
 - Switching from bit bang to a hardware based ssc frees
   up CPU time for other tasks e.g. demodulation
 2018-08-12 09:59:48 +02:00
Andreas Dröscher
c59150657c add: xcorr 211.875 kHz option 
The FPGA supported this frequency for a long time, just the ARM code
had no define to enable it.
 2018-08-12 09:59:48 +02:00
Andreas Dröscher
db70ab8f7d change: remove broken legic simulator 
It will be rewritten in a later commit
 2018-08-12 09:59:48 +02:00
Andreas Dröscher
8a53137ab0 change: remove dead legic code 
This code was either disabled or never reached.
 2018-08-12 09:59:48 +02:00
Andreas Dröscher
e779f06c5e change: clean up Legic interface 
I see no adventage in poluting all sources that include legicrf.h
with our internal depedencies (includes) and function names.
 2018-08-12 09:59:48 +02:00
Iceman
c339035ec5
Revert "WIP: Clean Legic Reader" 2018-08-06 15:05:36 +02:00
Andreas Dröscher
058426fa17 change: added rx/tx coordination timestamp 2018-08-05 00:57:20 +02:00
Andreas Dröscher
8f797d1388 change: legic reader tx back to bigbang 
I've tried to modulate the Legic specific pause-puls using ssc and the default
ssc clock of 105.4 kHz (bit periode of 9.4us) - previous commit. However,
the timing was not precise enough. By increasing the ssc clock this could
be circumvented, but the adventage over bitbang would be little.
 2018-08-05 00:57:20 +02:00
Andreas Dröscher
78d5188922 change: legic reader now uses xcorrelation and ssc based io 
- Even tough legic tags transmit just AM using xcorrelation
   results in a significantly better signal quality.
 - Switching from bit bang to a hardware based ssc frees
   up CPU time for other tasks e.g. demodulation
 2018-08-04 23:13:17 +02:00
Andreas Dröscher
d7c57dbc08 add: xcorr 211.875 kHz option 
The FPGA supported this frequency for a long time, just the ARM code
had no define to enable it.
 2018-08-04 23:13:17 +02:00
Andreas Dröscher
1adff322b1 change: remove broken legic simulator 
It will be rewritten in a later commit
 2018-08-04 23:13:17 +02:00
Andreas Dröscher
33eb2f5fa0 change: remove dead legic code 
This code was either disabled or never reached.
 2018-08-04 23:13:17 +02:00
Andreas Dröscher
37867fbf3b change: clean up Legic interface 
I see no adventage in poluting all sources that include legicrf.h
with our internal depedencies (includes) and function names.
 2018-08-04 23:13:17 +02:00
Chris
bacf8aff0f add: FPC connector skeleton usart. Not working but if will be a starting point for those who might want to help out with it. 2018-07-30 09:54:44 +02:00
iceman1001
08d9d9daf9 cleaning 2018-07-29 18:20:56 +02:00
iceman1001
c082531110 fix: potential implicit type cast issue (Thanks to @drandreas for pointing it out) 2018-07-29 18:20:39 +02:00
iceman1001
506da3ff4c textual 2018-07-29 16:30:36 +02:00
iceman1001
4172ea6c19 cleanup 2018-07-28 14:26:37 +02:00
iceman1001
4d8488e14b CHG: https://github.com/Proxmark/proxmark3/pull/631 from offical repo. (piwi) 
CHG: textual adjustments
 2018-07-28 14:25:12 +02:00
Chris
afeb0d0cd7 fix: removes unneeded floating point lib inclusion (@piwi) 2018-07-23 21:02:13 +02:00
Chris
fff2f51cfb chg: testing to switch from WaitXX calls to SpinDelay, they seem to mess up 2018-07-06 09:10:13 +02:00
Chris
79158c7360 chg; preparing for more cmds. 2018-07-06 00:24:04 +02:00
Chris
36d774506c chg: 'sm raw' - implemented 'r' don't read reply 2018-07-05 21:10:21 +02:00
Chris
2ccbde8110 chg: 'flashmem' - adjust debugstatemnts 2018-07-05 20:29:16 +02:00
Chris
fca841122f chg: 'sc reader' - hooked up atr. 2018-07-05 16:32:10 +02:00
Chris
ee006c6a7b add: sc upgrade - beta test 2018-07-05 14:38:31 +02:00
Chris
e7342e7402 chg: 'sc upgr' shouldnt print too much 2018-07-05 11:37:04 +02:00
Chris
f70b8be5de add: 'sc' - smart card commad [rdv40] 
chg: test to read out firmware
 2018-07-05 10:48:24 +02:00
Chris
3ecff83de2 chg: clean up 2018-07-04 15:29:27 +02:00
Chris
9571cf1d13 chg: and wrap FPC code with defines.. 2018-07-04 13:05:23 +02:00
Chris
a32052b5e6 chg: and remove link to FPC code 2018-07-04 13:01:53 +02:00
Chris
392161e20e chg: don't compile FPC yet 2018-07-04 12:58:28 +02:00
Chris
8f06f85cc4 DEL: removed old smartcard files 2018-07-04 12:22:12 +02:00
Chris
49735b62f1 syntax sugar 2018-07-04 12:20:08 +02:00
Chris
adb9e94487 chg: OR values 2018-07-04 12:19:29 +02:00
Chris
e09f9cbb32 add: RDV40 smart card module comms ( Thanks to @Willok! ) bitbanging i2c with it 2018-07-04 12:19:04 +02:00
Chris
ed5367a124 chg: adjusting 14b demod to increase reading distance 2018-06-30 22:48:59 +02:00
Chris
2b294912ee chg: 'hf iclass chk' - enabled credit/debit key selction 
chg:  'hf iclass lookup'  - enabled credit/debit key selction
fix: first item in dictionary file now correct identified
chg: code cleanup
 2018-06-30 22:47:07 +02:00
Chris
abdd51b6b3 chg: 'hf mf sim' led 2018-06-23 06:31:42 +02:00
Chris
4633e2083a debug 2018-06-23 06:30:47 +02:00
Chris
28a4260ee9 chg: 14b fixes 2018-06-19 12:57:27 +02:00
Chris
d9e8b63363 chg: setting pins 2018-06-13 14:38:46 +02:00
iceman1001
bd857b263f syntax 2018-05-22 12:10:02 +02:00