RfidResearchGroup/proxmark3
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18735 commits 3 branches 14 tags 85 MiB
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140 commits

Author SHA1 Message Date
iceman1001 b50d921be3 own compiled 2024-02-03 16:11:00 +01:00
Christian Zietz 225bb420c6 Shorten threshold registers to number of used bits 2024-02-03 12:09:02 +01:00
Christian Zietz dbfd8b7a6d Make detection threshold for ISO14443A configurable 
This adds a new command "hw sethfthresh" to configure the thresholds
used inside the FPGA while demodulating ISO14443A. The thresholds
need to be increased on particularly noisy hardware, such as certain
Chinese PM3 Easy clones.
 2024-02-02 20:51:05 +01:00
iceman1001 e4835e69a3 recompiled the fpga images 2024-01-24 17:06:41 +01:00
Yann GASCUEL c27cf92b76 iso15sniff: enable lowsignal sniffing 2024-01-24 13:59:12 +01:00
Yann GASCUEL fa3c2e386b improve iso15 sniff quality 2024-01-24 13:59:12 +01:00
iceman1001 0c4a1066c1 text 2024-01-05 19:27:38 +01:00
Philippe Teuwen d74e264250 style 2023-09-07 20:13:18 +02:00
iceman1001 85aac72855 new fpga images 2023-08-29 16:46:52 +02:00
Alex 762c942e95 Redundant check 
A 3 bit counter will naturally roll over to zero on overflow, there is no need to explicitly check for max value and manually reset to zero
 2023-08-29 11:26:43 +02:00
Alex 61765cc933 More compact notation 2023-08-29 11:24:56 +02:00
iceman1001 ba320f26f7 ensure registers and vars is set correct 2023-08-28 15:34:36 +02:00
iceman1001 114dda1582 After testing and verification its found that the SHALLOW MODULATION in HF is not working well in RDV4. Swapping from PWR_OE4 to PWR_OE1 makes it much better. Thanks to @d18c7db for solution and @gentlekiwi for testing and never giving up on finding the bug 2023-08-28 12:00:44 +02:00
Alex 3e4b7d07ff Whitespace, formatting 2023-08-24 18:21:07 +02:00
Alex 66b1758278 Removed commented out includes 
Include statements in individual files are not required when compiling the code the correct way as a project with an explicitly defined work library. The Makefile exactly replicates the compilation process of the ISE environment and generates the required project files.
 2023-08-24 18:06:44 +02:00
Alex c41c685807 Merged hi_reader and hi_reader_15 into one file 
hi_reader_15  was a superset of hi_reader, now uses conditional compile from Makefile like the other files to select compilations options
 2023-08-24 17:52:12 +02:00
iceman1001 71023d0c6e regenerated with the HF update 2023-07-12 16:25:14 +02:00
iceman1001 92f4ec08ab I tend to get better Mifare functionality. tested 6,7,8 and seven gave me better results 2023-07-12 16:09:28 +02:00
iceman1001 e43f6804a1 style 2023-07-06 22:37:34 +02:00
d18c7db c59bdec4f2 Unified fpga folders 2023-05-30 19:47:27 +02:00
Philippe Teuwen e79fb92074 Add fpga-xc3s100e and icopyx support 2021-08-21 23:45:46 +02:00
Philippe Teuwen 491adacb94 get rid of tabs 2020-10-06 20:45:13 +02:00
Philippe Teuwen 3f9ddf9b29 make style 2020-10-06 18:41:15 +02:00
iceman1001 8e5a285099 textual 2020-10-02 19:42:47 +02:00
iceman1001 7eadc900c1 pwr_oe2 is LF 2020-10-02 19:42:19 +02:00
iceman1001 cf3b18605f correction of text 2020-10-01 23:49:01 +02:00
iceman1001 a2abfb44ae correction of text 2020-10-01 23:48:32 +02:00
Philippe Teuwen c03e26cf57 Revert "tune stype exceptions" 
This reverts commit aff439953f.
 2020-08-13 12:48:46 +02:00
Philippe Teuwen aff439953f tune stype exceptions 2020-08-13 12:33:27 +02:00
Philippe Teuwen 4ed57c7c4d make style 2020-08-13 12:25:04 +02:00
iceman1001 ec1c72d73c fix felica image 2020-07-08 23:11:11 +02:00
iceman1001 2c0f595f86 no more snooping around 2020-07-03 14:59:10 +02:00
iceman1001 e2f0f08202 added felica bit file 2020-07-02 11:52:16 +02:00
iceman1001 fdd0487c37 updated bit files 2020-07-02 11:51:52 +02:00
iceman1001 da947affeb felica fpga scr file 2020-07-02 11:51:07 +02:00
iceman1001 59836bbb3b remove 2020-07-02 11:50:01 +02:00
iceman1001 081f397ed7 remove 2020-07-02 11:49:46 +02:00
iceman1001 41dde3281d add files 2020-07-02 11:49:22 +02:00
iceman1001 8df14408b8 fgpa changes from official repo. Had to split felica into its own image. Leading to three bit files created. 2020-07-02 11:47:46 +02:00
iceman1001 3f0f08ffbb updated fpga lf image for hitag 2020-02-22 13:34:52 +01:00
Philippe Teuwen af7fb17607 plotedge script: warn for numpy, matplotlib 2020-02-21 16:10:18 +01:00
Philippe Teuwen 15b661dbfb plot_edgedetect.py converted to python3 2020-02-21 15:36:12 +01:00
iceman1001 d6f552e856 assign direct 2020-01-28 22:06:40 +01:00
iceman1001 6fa188062c style 2020-01-12 17:30:29 +01:00
iceman1001 2e37c04a15 Add: 'hf plot' - implement function from offical repo (piwi) 2020-01-12 15:33:06 +01:00
iceman1001 e4bd3544d5 style 2020-01-12 00:31:08 +01:00
iceman1001 621eb12976 fix: lf simulation, wrong offsets in majormode 2020-01-12 00:30:23 +01:00
iceman1001 5b7882fc4f style 2020-01-12 00:19:12 +01:00
iceman1001 442bab0706 style 2020-01-12 00:18:34 +01:00
iceman1001 05f2fbc75a hitag adaptations (@anon) 2020-01-01 20:52:32 +01:00