17 commits

Author	SHA1	Message	Date
Philippe Teuwen	491adacb94	get rid of tabs	2020-10-06 20:45:13 +02:00
Philippe Teuwen	4ed57c7c4d	make style	2020-08-13 12:25:04 +02:00
iceman1001	8df14408b8	fgpa changes from official repo. Had to split felica into its own image. Leading to three bit files created.	2020-07-02 11:47:46 +02:00
Philippe Teuwen	1354aec556	typos	2019-08-06 13:51:10 +02:00
Philippe Teuwen	cb439ef58b	style of .v files	2019-07-30 22:51:38 +02:00
Philippe Teuwen	84f696451d	units	2019-05-09 01:07:34 +02:00
AntiCat	e472a21194	FPGA Hi-Simulate: Added 212kHz SSP-Clock option	2018-09-05 23:01:55 +02:00
AntiCat	0994c91888	FPGA Hi-Simulate: Freed up 4 LUTs	2018-09-05 23:01:55 +02:00
AntiCat	cef5dc4e83	FPGA Hi-Simulate: Fixed documantation	2018-09-05 23:01:55 +02:00
AntiCat	6ca899d130	FPGA Hi-Simulate: Formatted code	2018-09-05 23:01:55 +02:00
iceman1001	4b63f940f1	CHG: FeliCa implemenation by @satsuoni	2017-10-20 20:27:44 +02:00
iceman1001	496b673453	Added some comments	2017-01-26 14:23:48 +01:00
Martin Holst Swende	645c960f61	Implemented new FPGA mode for iclass tag simulation. Reduces arm-side size of transfer/memory by a factor of 8. Makes for easier arm-side encoding of messages, for when we start needing to do that on the fly instead of using precalculated messages	2015-01-15 15:16:34 +01:00
Martin Holst Swende	12401d8dbc	Added 424KHz mode for iso 15693 simulation	2014-06-07 21:39:52 +02:00
bushing	ba06a4b694	setting svn:eol-style=native on files, part 3 ... (should be done now, sorry)	2010-02-22 19:29:05 +00:00
henryk@ploetzli.ch	ecf53cb215	Add HF simulator modulation mode for 212kHz subcarrier	2009-10-12 07:46:03 +00:00
edouard@lafargue.name	6658905f18	Initial commit for the firmware. Used the 20090306_ela version as baseline. ... It is identical to the popular 20081211, with the doob addition (20090301), a linux client, and two additional commands for LF analysis. Let me know if you find issues here!	2009-04-09 06:43:20 +00:00