12 commits

Author	SHA1	Message	Date
Philippe Teuwen	d74e264250	style	2023-09-07 20:13:18 +02:00
Alex	3e4b7d07ff	Whitespace, formatting	2023-08-24 18:21:07 +02:00
d18c7db	c59bdec4f2	Unified fpga folders	2023-05-30 19:47:27 +02:00
Philippe Teuwen	e79fb92074	Add fpga-xc3s100e and icopyx support	2021-08-21 23:45:46 +02:00
iceman1001	7eadc900c1	pwr_oe2 is LF	2020-10-02 19:42:19 +02:00
iceman1001	8df14408b8	fgpa changes from official repo. Had to split felica into its own image. Leading to three bit files created.	2020-07-02 11:47:46 +02:00
iceman1001	6fa188062c	style	2020-01-12 17:30:29 +01:00
iceman1001	5b7882fc4f	style	2020-01-12 00:19:12 +01:00
Philippe Teuwen	cb439ef58b	style of .v files	2019-07-30 22:51:38 +02:00
iceman1001	f3ebfcb9a0	chg: reverting old @satsuoni felica changes. ... chg: applied @pwpiwi 's fixes for iso 14B / 15	2017-10-23 21:56:47 +02:00
iceman1001	4b63f940f1	CHG: FeliCa implemenation by @satsuoni	2017-10-20 20:27:44 +02:00
iceman1001	5c1f7686f6	ADD: FPGA code to support FeliCa / ISO 18092. Thanks to @satsuoni	2017-10-10 14:01:58 +02:00