Philippe Teuwen 2f12e57408 Makefiles: remove spurious spaces/tabs		2019-03-10 11:35:03 +01:00
..
tests	Makefiles: remove spurious spaces/tabs	2019-03-10 11:35:03 +01:00
clk_divider.v
fpga.ucf
fpga_hf.bit	FPGA Hi-Simulate: Added 212kHz SSP-Clock option	2018-09-05 23:01:55 +02:00
fpga_hf.v
fpga_lf.bit	FIX: LF antenna discharge after interfer timings. As suggested by @ts And thanks to @drandreas who patiently explains fpga verilog code to me.	2018-09-08 14:11:51 +02:00
fpga_lf.v	fix: variable name	2018-09-08 14:15:05 +02:00
go.bat	THIS REQUIRES A BOOTROM UPDATE!! To save FPGA area, split the LF and HF bitstreams and load them on-demand.	2014-06-20 01:02:59 +02:00
hi_flite.v
hi_iso14443a.v
hi_read_rx_xcorr.v
hi_read_tx.v	change: remove jerry-riged hysteresis based receiver from hi_read_tx	2018-08-12 09:59:48 +02:00
hi_simulate.v	FPGA Hi-Simulate: Added 212kHz SSP-Clock option	2018-09-05 23:01:55 +02:00
hi_sniffer.v
lf_edge_detect.v	New LF edge detection algorithm + lowpass filter	2014-06-27 14:27:03 +02:00
lo_edge_detect.v
lo_passthru.v
lo_read.v
lo_simulate.v
lp20khz_1MSa_iir_filter.v
Makefile	Makefiles: remove spurious spaces/tabs	2019-03-10 11:35:03 +01:00
min_max_tracker.v	fpga/min_max_tracker.v: english	2014-06-27 23:28:56 +02:00
sim.tcl
testbed_fpga.v
testbed_hi_read_tx.v
testbed_hi_simulate.v
testbed_lo_read.v
testbed_lo_simulate.v
util.v	setting svn:eol-style=native on files, part 3	2010-02-22 19:29:05 +00:00
xst_hf.scr
xst_lf.scr
xst_nfc.scr