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tests
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New LF edge detection algorithm + lowpass filter
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2014-06-27 14:27:03 +02:00 |
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clk_divider.v
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THIS REQUIRES A BOOTROM UPDATE!! To save FPGA area, split the LF and HF bitstreams and load them on-demand.
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2014-06-20 01:02:59 +02:00 |
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fpga.ucf
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fpga_hf.bit
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FPGA Hi-Simulate: Added 212kHz SSP-Clock option
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2018-09-05 23:01:55 +02:00 |
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fpga_hf.v
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FIX: @satsuoni fixes with pm3 offical version.
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2017-10-25 13:59:49 +02:00 |
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fpga_lf.bit
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FIX: LF antenna discharge after interfer timings. As suggested by @ts And thanks to @drandreas who patiently explains fpga verilog code to me.
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2018-09-08 14:11:51 +02:00 |
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fpga_lf.v
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fix: variable name
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2018-09-08 14:15:05 +02:00 |
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go.bat
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THIS REQUIRES A BOOTROM UPDATE!! To save FPGA area, split the LF and HF bitstreams and load them on-demand.
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2014-06-20 01:02:59 +02:00 |
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hi_flite.v
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chg: reverting old @satsuoni felica changes.
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2017-10-23 21:56:47 +02:00 |
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hi_iso14443a.v
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CHG: Thanks to @pwpiwi , his latest adjustments to HF.
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2017-11-10 19:51:37 +01:00 |
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hi_read_rx_xcorr.v
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change: fixed xcorrelation for strong signal
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2018-08-10 02:36:04 +02:00 |
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hi_read_tx.v
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change: remove jerry-riged hysteresis based receiver from hi_read_tx
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2018-08-12 09:59:48 +02:00 |
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hi_simulate.v
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FPGA Hi-Simulate: Added 212kHz SSP-Clock option
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2018-09-05 23:01:55 +02:00 |
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hi_sniffer.v
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chg: reverting old @satsuoni felica changes.
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2017-10-23 21:56:47 +02:00 |
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lf_edge_detect.v
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New LF edge detection algorithm + lowpass filter
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2014-06-27 14:27:03 +02:00 |
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lo_edge_detect.v
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fix: (issue #72) LF simulation didn't work with lo_edge_detect.v
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2015-03-06 07:42:54 +01:00 |
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lo_passthru.v
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fpga/fpga_hf.v, fpga_lf.v, lo_edge_detect.v, lo_passthru.v, lo_read.v: copyright notice
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2014-06-20 12:38:58 +02:00 |
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lo_read.v
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new command "lf snoop" to snoop raw ADC values
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2014-06-21 21:33:54 +02:00 |
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lo_simulate.v
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lp20khz_1MSa_iir_filter.v
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New LF edge detection algorithm + lowpass filter
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2014-06-27 14:27:03 +02:00 |
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Makefile
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FIX: @satsuoni fixes with pm3 offical version.
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2017-10-25 13:59:49 +02:00 |
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min_max_tracker.v
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fpga/min_max_tracker.v: english
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2014-06-27 23:28:56 +02:00 |
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sim.tcl
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testbed_fpga.v
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testbed_hi_read_tx.v
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testbed_hi_simulate.v
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testbed_lo_read.v
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testbed_lo_simulate.v
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util.v
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xst_hf.scr
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THIS REQUIRES A BOOTROM UPDATE!! To save FPGA area, split the LF and HF bitstreams and load them on-demand.
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2014-06-20 01:02:59 +02:00 |
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xst_lf.scr
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THIS REQUIRES A BOOTROM UPDATE!! To save FPGA area, split the LF and HF bitstreams and load them on-demand.
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2014-06-20 01:02:59 +02:00 |
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xst_nfc.scr
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ADD: FPGA missing file Thanks to @Satsuoni
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2017-10-10 14:03:09 +02:00 |
