Chris 1d51b2cd8f fix: variable name ... textual		2018-09-08 14:15:05 +02:00
..
tests
clk_divider.v
fpga.ucf
fpga_hf.bit	FPGA Hi-Simulate: Added 212kHz SSP-Clock option	2018-09-05 23:01:55 +02:00
fpga_hf.v	FIX: @satsuoni fixes with pm3 offical version.	2017-10-25 13:59:49 +02:00
fpga_lf.bit	FIX: LF antenna discharge after interfer timings. As suggested by @ts And thanks to @drandreas who patiently explains fpga verilog code to me.	2018-09-08 14:11:51 +02:00
fpga_lf.v	fix: variable name	2018-09-08 14:15:05 +02:00
go.bat
hi_flite.v	chg: reverting old @satsuoni felica changes.	2017-10-23 21:56:47 +02:00
hi_iso14443a.v	CHG: Thanks to @pwpiwi , his latest adjustments to HF.	2017-11-10 19:51:37 +01:00
hi_read_rx_xcorr.v	change: fixed xcorrelation for strong signal	2018-08-10 02:36:04 +02:00
hi_read_tx.v	change: remove jerry-riged hysteresis based receiver from hi_read_tx	2018-08-12 09:59:48 +02:00
hi_simulate.v	FPGA Hi-Simulate: Added 212kHz SSP-Clock option	2018-09-05 23:01:55 +02:00
hi_sniffer.v	chg: reverting old @satsuoni felica changes.	2017-10-23 21:56:47 +02:00
lf_edge_detect.v
lo_edge_detect.v
lo_passthru.v
lo_read.v
lo_simulate.v
lp20khz_1MSa_iir_filter.v
Makefile	FIX: @satsuoni fixes with pm3 offical version.	2017-10-25 13:59:49 +02:00
min_max_tracker.v
sim.tcl
testbed_fpga.v
testbed_hi_read_tx.v
testbed_hi_simulate.v
testbed_lo_read.v
testbed_lo_simulate.v
util.v
xst_hf.scr
xst_lf.scr
xst_nfc.scr	ADD: FPGA missing file Thanks to @Satsuoni	2017-10-10 14:03:09 +02:00