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1297 commits

Author SHA1 Message Date
Chris ba9de80eeb chg: 'hf legic sim' break sim by sending another cmd 2018-09-09 11:29:11 +02:00
Chris 79afc031fc FIX: LF antenna discharge after interfer timings. As suggested by @ts And thanks to @drandreas who patiently explains fpga verilog code to me. 
This introduces a new majoe mode, FPGA_MAJOR_MODE_OFF_LF,  which should ONLY be used in sending loops for LF.   Basically the PWR_LO is set HIGH in order to discharge voltage faster.

Once sending is over,  the normal FPGA_MAJOR_MODE_OFF SHALL be used.
 2018-09-08 14:11:51 +02:00
Chris e5e8c0b5d8 not needed anymore 2018-09-07 23:45:08 +02:00
Chris 24eaac8681 CHG: the thread comms refactoring from offical pm3 repo 
chg: FPC com speed limited to 115200 when compiled with FPC
chg: USART remake (@drandreas)
 2018-09-06 21:43:20 +02:00
RFID Research Group eb0b5116a2
Merge pull request #25 from drandreas/rdv4-legic 
Legic Tag Simulator
 2018-09-06 20:26:39 +02:00
Colin J. Brigato 7e12fc0ceb Pass 2; commit 3/3; 2018-09-06 05:34:48 +02:00
Colin J. Brigato 368fe11df0 Second Pass rewrite of flashmem. added command 'mem spibaud' to switch between 24/48Mhz operation. All is more consistant, less messy. All logic rewrittent avoiding multiple flashinit/flashstop. busywait is now at it's lowest possible. Beware : 48Mhz is VERY buggy cause of sillicon bug (see source for more info), and doesn't give much more than 24Mhz for now since we doubled nearly every operation speed here. 2018-09-06 05:15:52 +02:00
AntiCat e1fa1e659a Legic: Implemented write command for card simulation 2018-09-05 23:03:05 +02:00
AntiCat 2981fe7ce8 Legic: Implemented read command for card simulation 2018-09-05 23:03:05 +02:00
AntiCat cd78b00815 Legic: Implemented setup phase for card simulation 2018-09-05 23:03:05 +02:00
AntiCat 2c6c4e5bc6 Legic: Implemented trace log 2018-09-05 23:03:05 +02:00
AntiCat fe91a3f52f Legic: Implemented RX and TX for card simulation 2018-09-05 23:03:05 +02:00
AntiCat 61e4eac2b2 Legic: Moved card simulator into separate file & cleaned interface. 
Reader and card simulation have almost no common code. Moreover the sim
uses an SSP Clock at 212kHz for all timings to prevent any drifting from
the PRNG. This clock speed is not available in reader simulation mode (SSP
runs at up to 3.4MHz, and changes speed between TX and RX). For these
reasons having the code in separate files makes it significantly cleaner.
 2018-09-05 23:03:04 +02:00
Colin J. Brigato 76e2d7502a Merge remote-tracking branch 'upstream/master' 2018-09-05 20:39:56 +02:00
Colin J. Brigato 2263c826db Restore Makefile, temporiraly provide Makefile.Colin 2018-09-05 20:34:28 +02:00
Chris 4c72acaf63 FIX: cleanup code, sync of output texts. 2018-09-05 18:58:58 +02:00
Chris 4c37126baf cleanup 2018-09-05 18:58:04 +02:00
def b7bdc69e5a lfops.c CmdEM410xdemod empty TAG ID fix. 2018-09-05 17:50:31 +03:00
Chris 307063474d CHG: cleanup 2018-09-04 20:36:25 +02:00
Chris ac6bd61544 FIX: longer t55xx timings to compensate for delay of field damping, and minor adjustments. 2018-09-04 20:35:29 +02:00
Chris e12d22b6d9 FIX: 'LF Standalone modes' - Ensure that noise check is performed for any device-side processing otherwise device-side processing will see all LF signals as noise. 
From: 8bddce8096
 2018-09-04 20:32:52 +02:00
Chris 27a036b087 FIX: logic behind compiler directive is now correct 2018-09-04 20:31:12 +02:00
Iceman 701b96d7fe
Update readme.md 2018-09-03 22:45:01 +02:00
Chris 76e7603ef1 textual 2018-09-03 22:36:43 +02:00
Chris 0e3ba1c058 CHG: easier to configure compilation of standalone mode. Just swap -D directive once your new standalone mode is ready and you added your code for it 
based on a modification by @marshmellow42
 2018-09-03 22:27:18 +02:00
Colin J. Brigato 8d673fa1bf First pass rewrite of flashmem driver for optimization. Lot of changes here. Provides PoC of saving and recalling a tag in Standalone mode. Added some printing passthrough to client to azccomodate for vt100 eye-candyness. FastREAD mode implemented for flashmem, testable from client. Beta but functionnal. Reading the whole flash with 1Kb to 32kb buffers was ~730ms, now 380ms Max (even at 24Mhz spi baudrate) 2018-09-03 00:02:44 +02:00
Chris f1d0e9db4d fix: revert back 2018-08-29 19:42:46 +02:00
Chris 42e883f67b FIX: print_result - now prints correct len. 
FIX: DOWNLOAD_BUFFER -  now with correct result logic
 2018-08-28 21:15:28 +02:00
Chris ca5b476730 FIX: 'standanlonemode colin' - mifare1ksim called with correct params (@cjbrigato) 2018-08-26 08:19:59 +02:00
Chris 2eab02e3ba CHG: 'standalone mode MattyRun' - added some comments and suggestion 2018-08-25 23:26:04 +02:00
Chris fe332a1f2b removed unneeded ramfunc attribute 2018-08-13 23:50:17 +02:00
Chris 91dea8d694 code clean. 2018-08-13 23:49:33 +02:00
Chris 5f77121694 initial commit to be in sync the-soon-defunct repo pm3rdv40. 2018-08-12 21:54:31 +02:00
Andreas Dröscher 9ba20b590a change: reduced demodulator to bare minimum 
The initial code added complexity without improving reading distance.
Thankfully the peak detection signal path has a low noise floor.
 2018-08-12 12:51:45 +02:00
Andreas Dröscher 0d0b651246 change: re-added trace log 2018-08-12 12:51:45 +02:00
Andreas Dröscher ff5b046903 change: re-added status LEDs 
- LED_A: FPGA and 13.56MHz carrier is active
- LED_B: Reading Byte
- LED_C: Writing Byte
 2018-08-12 12:41:45 +02:00
Andreas Dröscher e052fbc433 change: re-added legic write support 2018-08-12 12:41:45 +02:00
Andreas Dröscher 9d330dde87 fix: 32bit tick timer based on TC0 and TC1 
TC1 counts the number of TC0 overflows (carry bits).
In random conditions TC1 would return or stay at zero,
instead of counting up. This due to the behavior of the
reset signal.

SAM7S Series Datasheet, 33.5.6 Trigger:
Regardless of the trigger used, it will be taken into account
at the following active edge of the selected clock. This means
that the counter value can be read differently from zero just
after a trigger, especially when a low frequency signal is
selected as the clock.

The new code first prepares TC1 and asserts TC1 trigger and
then prepares TC0 and asserts TC0 trigger. The TC0 start-up
will reset TC1.
 2018-08-12 12:41:11 +02:00
Andreas Dröscher c06f0af7f3 change: switched from timestamps (us) to ticks 
GetCountUS() has a jitter of +/- 7us this is not precise
enough to keep the PRNG in sync. 1.5 * GET_TICKS on the
other hand is spot on.
 2018-08-12 09:59:48 +02:00
Andreas Dröscher e0adc976e0 change: added rx/tx coordination timestamp 2018-08-12 09:59:48 +02:00
Andreas Dröscher 7244f5825d change: legic reader tx back to bigbang 
I've tried to modulate the Legic specific pause-puls using ssc and the default
ssc clock of 105.4 kHz (bit periode of 9.4us) - previous commit. However,
the timing was not precise enough. By increasing the ssc clock this could
be circumvented, but the adventage over bitbang would be little.
 2018-08-12 09:59:48 +02:00
Andreas Dröscher 3029223158 change: legic reader now uses xcorrelation and ssc based io 
- Even tough legic tags transmit just AM using xcorrelation
   results in a significantly better signal quality.
 - Switching from bit bang to a hardware based ssc frees
   up CPU time for other tasks e.g. demodulation
 2018-08-12 09:59:48 +02:00
Andreas Dröscher c59150657c add: xcorr 211.875 kHz option 
The FPGA supported this frequency for a long time, just the ARM code
had no define to enable it.
 2018-08-12 09:59:48 +02:00
Andreas Dröscher db70ab8f7d change: remove broken legic simulator 
It will be rewritten in a later commit
 2018-08-12 09:59:48 +02:00
Andreas Dröscher 8a53137ab0 change: remove dead legic code 
This code was either disabled or never reached.
 2018-08-12 09:59:48 +02:00
Andreas Dröscher e779f06c5e change: clean up Legic interface 
I see no adventage in poluting all sources that include legicrf.h
with our internal depedencies (includes) and function names.
 2018-08-12 09:59:48 +02:00
Iceman c339035ec5
Revert "WIP: Clean Legic Reader" 2018-08-06 15:05:36 +02:00
Andreas Dröscher 058426fa17 change: added rx/tx coordination timestamp 2018-08-05 00:57:20 +02:00
Andreas Dröscher 8f797d1388 change: legic reader tx back to bigbang 
I've tried to modulate the Legic specific pause-puls using ssc and the default
ssc clock of 105.4 kHz (bit periode of 9.4us) - previous commit. However,
the timing was not precise enough. By increasing the ssc clock this could
be circumvented, but the adventage over bitbang would be little.
 2018-08-05 00:57:20 +02:00
Andreas Dröscher 78d5188922 change: legic reader now uses xcorrelation and ssc based io 
- Even tough legic tags transmit just AM using xcorrelation
   results in a significantly better signal quality.
 - Switching from bit bang to a hardware based ssc frees
   up CPU time for other tasks e.g. demodulation
 2018-08-04 23:13:17 +02:00
Andreas Dröscher d7c57dbc08 add: xcorr 211.875 kHz option 
The FPGA supported this frequency for a long time, just the ARM code
had no define to enable it.
 2018-08-04 23:13:17 +02:00
Andreas Dröscher 1adff322b1 change: remove broken legic simulator 
It will be rewritten in a later commit
 2018-08-04 23:13:17 +02:00
Andreas Dröscher 33eb2f5fa0 change: remove dead legic code 
This code was either disabled or never reached.
 2018-08-04 23:13:17 +02:00
Andreas Dröscher 37867fbf3b change: clean up Legic interface 
I see no adventage in poluting all sources that include legicrf.h
with our internal depedencies (includes) and function names.
 2018-08-04 23:13:17 +02:00
Chris bacf8aff0f add: FPC connector skeleton usart. Not working but if will be a starting point for those who might want to help out with it. 2018-07-30 09:54:44 +02:00
iceman1001 08d9d9daf9 cleaning 2018-07-29 18:20:56 +02:00
iceman1001 c082531110 fix: potential implicit type cast issue (Thanks to @drandreas for pointing it out) 2018-07-29 18:20:39 +02:00
iceman1001 506da3ff4c textual 2018-07-29 16:30:36 +02:00
iceman1001 4172ea6c19 cleanup 2018-07-28 14:26:37 +02:00
iceman1001 4d8488e14b CHG: https://github.com/Proxmark/proxmark3/pull/631 from offical repo. (piwi) 
CHG: textual adjustments
 2018-07-28 14:25:12 +02:00
Chris afeb0d0cd7 fix: removes unneeded floating point lib inclusion (@piwi) 2018-07-23 21:02:13 +02:00
Chris fff2f51cfb chg: testing to switch from WaitXX calls to SpinDelay, they seem to mess up 2018-07-06 09:10:13 +02:00
Chris 79158c7360 chg; preparing for more cmds. 2018-07-06 00:24:04 +02:00
Chris 36d774506c chg: 'sm raw' - implemented 'r' don't read reply 2018-07-05 21:10:21 +02:00
Chris 2ccbde8110 chg: 'flashmem' - adjust debugstatemnts 2018-07-05 20:29:16 +02:00
Chris fca841122f chg: 'sc reader' - hooked up atr. 2018-07-05 16:32:10 +02:00
Chris ee006c6a7b add: sc upgrade - beta test 2018-07-05 14:38:31 +02:00
Chris e7342e7402 chg: 'sc upgr' shouldnt print too much 2018-07-05 11:37:04 +02:00
Chris f70b8be5de add: 'sc' - smart card commad [rdv40] 
chg: test to read out firmware
 2018-07-05 10:48:24 +02:00
Chris 3ecff83de2 chg: clean up 2018-07-04 15:29:27 +02:00
Chris 9571cf1d13 chg: and wrap FPC code with defines.. 2018-07-04 13:05:23 +02:00
Chris a32052b5e6 chg: and remove link to FPC code 2018-07-04 13:01:53 +02:00
Chris 392161e20e chg: don't compile FPC yet 2018-07-04 12:58:28 +02:00
Chris 8f06f85cc4 DEL: removed old smartcard files 2018-07-04 12:22:12 +02:00
Chris 49735b62f1 syntax sugar 2018-07-04 12:20:08 +02:00
Chris adb9e94487 chg: OR values 2018-07-04 12:19:29 +02:00
Chris e09f9cbb32 add: RDV40 smart card module comms ( Thanks to @Willok! ) bitbanging i2c with it 2018-07-04 12:19:04 +02:00
Chris ed5367a124 chg: adjusting 14b demod to increase reading distance 2018-06-30 22:48:59 +02:00
Chris 2b294912ee chg: 'hf iclass chk' - enabled credit/debit key selction 
chg:  'hf iclass lookup'  - enabled credit/debit key selction
fix: first item in dictionary file now correct identified
chg: code cleanup
 2018-06-30 22:47:07 +02:00
Chris abdd51b6b3 chg: 'hf mf sim' led 2018-06-23 06:31:42 +02:00
Chris 4633e2083a debug 2018-06-23 06:30:47 +02:00
Chris 28a4260ee9 chg: 14b fixes 2018-06-19 12:57:27 +02:00
Chris d9e8b63363 chg: setting pins 2018-06-13 14:38:46 +02:00
iceman1001 bd857b263f syntax 2018-05-22 12:10:02 +02:00
iceman1001 501c29f76d add: support for reading flashmem 2018-05-22 12:09:17 +02:00
iceman1001 6b7819276d add: 'mem info' - rudamentary support for new command. 2018-05-06 09:26:06 +02:00
iceman1001 110a7b28cb chg: 'hf 14a sim' - possibility to simulate FM11RF005SH (@maozhenyu123) 
chg: 'hf 14a info' - tag identification for FM11RF005SH (@maozhenyu123)

Fudan FM11RF005SH , has 512bit mem,  16blocks w 4bytes / block.
Support REQA, READ, WRITE, AUTH.   Unknown how the auth is done.

The ATQA/SAK ,  or a trace from one of these tags would be intersting to look at.
 2018-05-06 09:24:28 +02:00
iceman1001 3e7576c86d fix: 'hf mfu rdbl' 
fix: 'hf mfu dump'  -  bad exit strategy
 2018-05-03 22:41:28 +02:00
iceman1001 4cd72b95c5 fix: coverty scan #277726, unsigned value comparision always true. 2018-05-03 20:36:01 +02:00
iceman1001 989b80007c chg: removed debugstatements 2018-05-03 16:20:46 +02:00
iceman1001 e50fef6607 fix: 'mem load' - wrong offset when uploading 2018-05-03 16:10:38 +02:00
iceman1001 021c0a1349 ADD: 'mem' commands. For RDV40 devices only. 
If you don't have one,  comment out inside client/Makefile this line

CFLAGS += -DWITH_FLASH
 2018-05-03 12:15:03 +02:00
iceman1001 207fa2b574 add: potential fix for OSX uses, by @piwi 
chg:  adapting fix to support iceman forks extended commands.
 2018-05-02 08:11:29 +02:00
iceman1001 98f0e9a284 fix: print.c on device doesn't have support for formatter %f 2018-04-27 12:16:35 +02:00
iceman1001 271cb3e1cc chg: \r didn't work well with printandlogex 
chg: spaces
chg: cleaning
 2018-04-27 12:15:26 +02:00
iceman1001 2017f321b7 fix: memory issue, took all bigbuff 2018-04-25 01:33:25 +02:00
iceman1001 695d4cbb51 chg: fix coverity scan bug, variable is treated like a array 2018-04-20 20:07:41 +02:00
iceman1001 6ab1b285a0 chg. 2018-04-20 19:50:56 +02:00
iceman1001 f5718fb448 chg: wiping / reading / writing flashmem 2018-04-20 16:11:10 +02:00
iceman1001 a746699f5f chg: reading / writing flashmem works better now. 2018-04-19 00:27:44 +02:00