Chris
79afc031fc
FIX: LF antenna discharge after interfer timings. As suggested by @ts And thanks to @drandreas who patiently explains fpga verilog code to me.
...
This introduces a new majoe mode, FPGA_MAJOR_MODE_OFF_LF, which should ONLY be used in sending loops for LF. Basically the PWR_LO is set HIGH in order to discharge voltage faster.
Once sending is over, the normal FPGA_MAJOR_MODE_OFF SHALL be used.
2018-09-08 14:11:51 +02:00
Chris
56f3ef2a55
chg: helptext (@drandreas)
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chg: 'hf legic esave' now saves to both BIN / EML
2018-09-08 12:38:36 +02:00
Chris
65b29410d4
chg.. space..
2018-09-08 11:23:17 +02:00
Chris
0e2dbe7424
chg: code cleanup
2018-09-08 11:18:10 +02:00
Chris
0b673683d9
fix: 'hf legic sim' no assign... (Thanks to @625)
2018-09-08 11:17:31 +02:00
Chris
e29bb51e76
chg;: idea of auto adjusting signal to zero mean baseline in order to compensate different antennas
2018-09-07 23:47:42 +02:00
Chris
51fdde0bbf
code clean
2018-09-07 23:46:44 +02:00
Chris
b7d0786ab8
code clean
2018-09-07 23:45:52 +02:00
Chris
e5e8c0b5d8
not needed anymore
2018-09-07 23:45:08 +02:00
Chris
bb5804b1b0
text
2018-09-06 21:47:57 +02:00
Chris
3a338f566e
chg: zero mean in hidfskdemod
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chg: idteck demod return values
2018-09-06 21:44:53 +02:00
Chris
24eaac8681
CHG: the thread comms refactoring from offical pm3 repo
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chg: FPC com speed limited to 115200 when compiled with FPC
chg: USART remake (@drandreas)
2018-09-06 21:43:20 +02:00
RFID Research Group
eb0b5116a2
Merge pull request #25 from drandreas/rdv4-legic
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Legic Tag Simulator
2018-09-06 20:26:39 +02:00
RFID Research Group
5019f847a5
Merge pull request #21 from cjbrigato/master
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[Updated] Flashmem optimization, pass 1 + 2
2018-09-06 17:27:26 +02:00
Colin J. Brigato
7e12fc0ceb
Pass 2; commit 3/3;
2018-09-06 05:34:48 +02:00
Colin J. Brigato
c74dbb63b8
Pass 2; commit 2;
2018-09-06 05:24:50 +02:00
Colin J. Brigato
368fe11df0
Second Pass rewrite of flashmem. added command 'mem spibaud' to switch between 24/48Mhz operation. All is more consistant, less messy. All logic rewrittent avoiding multiple flashinit/flashstop. busywait is now at it's lowest possible. Beware : 48Mhz is VERY buggy cause of sillicon bug (see source for more info), and doesn't give much more than 24Mhz for now since we doubled nearly every operation speed here.
2018-09-06 05:15:52 +02:00
AntiCat
e1fa1e659a
Legic: Implemented write command for card simulation
2018-09-05 23:03:05 +02:00
AntiCat
2981fe7ce8
Legic: Implemented read command for card simulation
2018-09-05 23:03:05 +02:00
AntiCat
cd78b00815
Legic: Implemented setup phase for card simulation
2018-09-05 23:03:05 +02:00
AntiCat
2c6c4e5bc6
Legic: Implemented trace log
2018-09-05 23:03:05 +02:00
AntiCat
fe91a3f52f
Legic: Implemented RX and TX for card simulation
2018-09-05 23:03:05 +02:00
AntiCat
61e4eac2b2
Legic: Moved card simulator into separate file & cleaned interface.
...
Reader and card simulation have almost no common code. Moreover the sim
uses an SSP Clock at 212kHz for all timings to prevent any drifting from
the PRNG. This clock speed is not available in reader simulation mode (SSP
runs at up to 3.4MHz, and changes speed between TX and RX). For these
reasons having the code in separate files makes it significantly cleaner.
2018-09-05 23:03:04 +02:00
AntiCat
e472a21194
FPGA Hi-Simulate: Added 212kHz SSP-Clock option
2018-09-05 23:01:55 +02:00
AntiCat
0994c91888
FPGA Hi-Simulate: Freed up 4 LUTs
2018-09-05 23:01:55 +02:00
AntiCat
cef5dc4e83
FPGA Hi-Simulate: Fixed documantation
2018-09-05 23:01:55 +02:00
AntiCat
6ca899d130
FPGA Hi-Simulate: Formatted code
2018-09-05 23:01:55 +02:00
Colin J. Brigato
76e2d7502a
Merge remote-tracking branch 'upstream/master'
2018-09-05 20:39:56 +02:00
Colin J. Brigato
2263c826db
Restore Makefile, temporiraly provide Makefile.Colin
2018-09-05 20:34:28 +02:00
Chris
972d30474d
Add 'rem' - new command that adds a line to the log file (@didierStevens)
2018-09-05 20:31:10 +02:00
Chris
4200ed5dc9
fix: justnoice
2018-09-05 19:16:49 +02:00
Chris
8b047ae9f5
cleanup
2018-09-05 19:13:39 +02:00
Chris
605d7a2343
FIX: just noice detection on device / client
2018-09-05 19:07:31 +02:00
Chris
4c72acaf63
FIX: cleanup code, sync of output texts.
2018-09-05 18:58:58 +02:00
Chris
4c37126baf
cleanup
2018-09-05 18:58:04 +02:00
Chris
fb49ca9735
FIX: em410xdemod empty tag id
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Code cleanup
2018-09-05 18:56:21 +02:00
RFID Research Group
761e0cd0f9
Merge pull request #24 from Defensor7/master
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lfops.c CmdEM410xdemod empty TAG ID fix.
2018-09-05 18:12:11 +02:00
def
b7bdc69e5a
lfops.c CmdEM410xdemod empty TAG ID fix.
2018-09-05 17:50:31 +03:00
Chris
b80d683ce6
Added new support str function
2018-09-04 20:39:15 +02:00
Chris
d458a4ec2e
textual
2018-09-04 20:37:43 +02:00
Chris
307063474d
CHG: cleanup
2018-09-04 20:36:25 +02:00
Chris
ac6bd61544
FIX: longer t55xx timings to compensate for delay of field damping, and minor adjustments.
2018-09-04 20:35:29 +02:00
Chris
e12d22b6d9
FIX: 'LF Standalone modes' - Ensure that noise check is performed for any device-side processing otherwise device-side processing will see all LF signals as noise.
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From: 8bddce8096
2018-09-04 20:32:52 +02:00
Chris
27a036b087
FIX: logic behind compiler directive is now correct
2018-09-04 20:31:12 +02:00
RFID Research Group
947e5bf461
Merge pull request #22 from iceman1001/patch-1
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Update readme.md
2018-09-03 22:45:36 +02:00
Iceman
701b96d7fe
Update readme.md
2018-09-03 22:45:01 +02:00
Chris
76e7603ef1
textual
2018-09-03 22:36:43 +02:00
Chris
0e3ba1c058
CHG: easier to configure compilation of standalone mode. Just swap -D directive once your new standalone mode is ready and you added your code for it
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based on a modification by @marshmellow42
2018-09-03 22:27:18 +02:00
Chris
2f8ea1a92c
Merge branch 'master' of https://github.com/RfidResearchGroup/proxmark3
2018-09-03 19:07:14 +02:00
Chris
ff16cbb4db
FIX: USB Device descriptor issue, (@micolous, @megabug)
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https://github.com/iceman1001/proxmark3/pull/243
1be25f9125
2018-09-03 19:04:53 +02:00
