Commit graph

26 commits

Author SHA1 Message Date
iceman1001
2e37c04a15 Add: 'hf plot' - implement function from offical repo (piwi) 2020-01-12 15:33:06 +01:00
iceman1001
621eb12976 fix: lf simulation, wrong offsets in majormode 2020-01-12 00:30:23 +01:00
AntiCat
e472a21194 FPGA Hi-Simulate: Added 212kHz SSP-Clock option 2018-09-05 23:01:55 +02:00
Andreas Dröscher
bf123082e8 change: remove jerry-riged hysteresis based receiver from hi_read_tx
This future got obsolete by a x-correlation based receiver.

This reverts commit 24fe4dffb4.
2018-08-12 09:59:48 +02:00
Andreas Dröscher
83a4259ddc change: fixed xcorrelation for strong signal
The initial code assumed phase shift modulation only. Lately,
xcorrelation is also used for load modulation. But the initial
the assumption that 11 bits are enough isn't true for load
modulation.

This change extends the registers by 2 bits and compresses the
uper bits to preserve the sensitivity on the lower end.
2018-08-10 02:36:04 +02:00
Iceman
c339035ec5
Revert "WIP: Clean Legic Reader" 2018-08-06 15:05:36 +02:00
Andreas Dröscher
78d5188922 change: legic reader now uses xcorrelation and ssc based io
- Even tough legic tags transmit just AM using xcorrelation
   results in a significantly better signal quality.
 - Switching from bit bang to a hardware based ssc frees
   up CPU time for other tasks e.g. demodulation
2018-08-04 23:13:17 +02:00
iceman1001
84b7ea82bb fix: legic functionality for RDV40. Getting 2-3cm reading distances now. 2018-07-28 18:45:13 +02:00
iceman1001
ccfcd8e991 CHG: Thanks to @pwpiwi , his latest adjustments to HF. 2017-11-10 19:51:37 +01:00
iceman1001
3fd792940b FIX: @satsuoni fixes with pm3 offical version. 2017-10-25 13:59:49 +02:00
iceman1001
c2444a885b CHG: FeliCa and 14b/15 enhancements. or it should be atleast. Until it gets tested.. 2017-10-24 18:24:30 +02:00
iceman1001
f3ebfcb9a0 chg: reverting old @satsuoni felica changes.
chg: applied @pwpiwi 's fixes for iso 14B / 15
2017-10-23 21:56:47 +02:00
iceman1001
4b63f940f1 CHG: FeliCa implemenation by @satsuoni 2017-10-20 20:27:44 +02:00
iceman1001
5c1f7686f6 ADD: FPGA code to support FeliCa / ISO 18092. Thanks to @satsuoni 2017-10-10 14:01:58 +02:00
iceman1001
1ef14f2d9d fix: the updated fpga_hf.bit file, where iso15693 should work. 2017-07-07 09:20:23 +02:00
iceman1001
f5d2e7f7df CHG: @ematrix / @piwi fixes for 'hf snoop' 2015-11-02 11:41:25 +01:00
iceman1001
eb4222d773 CHG: the updated fpga image for the "hf snoop" 2015-10-30 09:10:09 +01:00
pwpiwi
705bfa1058 fixing iso14443b (issue #103):
- increased DMA_BUFFER_SIZE to avoid occasional circular buffer overflows.
- minor code cleanups
2015-06-22 22:03:43 +02:00
pwpiwi
467340996e fixing iso14443b (issue #103):
- fix hf 14b snoop
- fix hf 14b sim
2015-06-21 18:04:24 +02:00
pwpiwi
da586b1702 fixing iso14443b (issue #103):
- revert removal of FPGA_HF_READER_RX_XCORR_848_KHZ. Need to be able to switch to 424kHz for ISO15693.
2015-06-18 15:41:30 +02:00
pwpiwi
51d4f6f114 fixing iso14443b (issue #103):
- fix: IQ demodulator (FPGA)
- fix: approximately align reader signal delay to tag response delay (FPGA)
- fix: remove deprecated RSSI calculation to improve decoder speed (iso14443b.c)
- fix: better approximation of signal amplitude to avoid false carrier detection (iso14443b.c)
- fix: remove initial power off in iso14443b raw command (iso14443b.c)
- add: enable tracing for iso14443b raw command (iso14443b.c)
- fix: client crashed when checking CRC for incomplete responses (iso14433b.c)
- speeding up snoop to avoid circular buffer overflow
- added some comments for better documentation
- rename functions (iso14443 -> iso14443b)
- remove unused code in hi_read_rx_xcorr.v
2015-06-17 20:27:36 +02:00
pwpiwi
5b95953d42 fixing iso14443b (issue #103):
- most significant bit of tag data (which happens to be the sign bit)
had been dropped when snooping (FPGA change)
- avoid trying to decode both tag and reader data when snooping (we don't
have the time to do so).
2015-06-02 22:50:16 +02:00
pwpiwi
30364d2711 fix: broken edge detector implementation in hi_iso14443a.v resulted in decreased sensitivity 2015-03-09 20:01:37 +01:00
pwpiwi
7554370c30 bugfix hf 14a sim / hf mf sim: polarity of tag subcarrier modulation was wrong 2015-02-11 21:14:34 +01:00
Martin Holst Swende
645c960f61 Implemented new FPGA mode for iclass tag simulation. Reduces arm-side size of transfer/memory by a factor of 8. Makes for easier arm-side encoding of messages, for when we start needing to do that on the fly instead of using precalculated messages 2015-01-15 15:16:34 +01:00
iZsh
7cc204bff8 THIS REQUIRES A BOOTROM UPDATE!! To save FPGA area, split the LF and HF bitstreams and load them on-demand. 2014-06-20 01:02:59 +02:00