* make fpga_version_info.c phony and delete it on 'make clean'
* wait for transfer to complete before returning from FpgaSendCommand()
* log correct tag times in iclass simulation
* shorten pulse from TC1 to TC0 in StartCountSspClk()
* shorten ssp_frame pulse in fpga/hi_reader.v
* some reformatting and whitespace fixes
* don't display error message during 'lf search' when no Hitag tag is present
* remove superfluous options in 'lf hitag read'
* fix setting of default threshold when selecting FPGA_CMD_SET_EDGE_DETECT_THRESHOLD major mode
* some refactoring
* fix long option --jam
* make room for one more bit for FPGA minor mode
* new mode FPGA_HF_READER_MODE_SEND_JAM
* implement jamming in Handle15693SampleFromReader
* code deduplication. Use functions from iso15693.c
* speedup CodeIso15693AsReader()
* invert reader command coding. 0 now means 'unmodulated' ( = field on)
* decode SOF only as a valid tag response in Handle15693SamplesFromTag()
* complete decoding of EOF in Handle15693SamplesFromTag()
* determine and write correct times to trace
* FPGA-change: generate shorter frame signal to allow proper sync in StartCountSspClk()
* modify StartCountSspClk() for 16bit SSC transfers
* whitespace in util.c
* add specific LogTrace_ISO15693() with scaled down duration. Modify cmdhflist.c accordingly.
* allow 'hf 15 raw' with single byte commands
* check for buffer overflow, card timeout and single SOF in 'hf 15 raw'
* fix tag response timing. iClass differs from ISO15693 in this respect.
* speedup CodeIso15693AsTag()
* TransmitTo15693Tag(): don't send unmodulated start of SOF
* reduce modulation depth in hi_simulate.v
* calculate CRC for configuration block when simulating
* Show real response time instead of planned response time in 'hf list iclass'
* chg to reader command decoder in iso15693.c (require no modulation before SOF)
* add 'has_been_low_for' logic to hi_simulate.v (same as in other FPGA modes, default to "no modulation")
* add simulation of chip status (IDLE, ACTIVE, SELECTED, HALTED)
* check ACSN on SELECT
* add simulation of RESELECT
* always check length of reader commands
* fix printing of NR, MAC in sim 2 mode
* fix response length to CHECK command
* merge hf_rx_xcorr and hf_tx modes into one module with common ssp_clk and ssp_frame
* get rid of most of the warnings when compiling the HF verilog sources
* refactoring the constants in Verilog sources
* Add raw HF signal plotting
* new fpga module hi_get_trace.v - store A/D converter output to circular buffer on FPGA
* new command 'hf plot' - pull data from FPGA and display it in Graph Window
* fixing hf 15: implement hf 15 snoop
* rename hf 15 record to hf 15 snoop
* speedup sampling / decoding:
* new FPGA mode FPGA_HF_READER_RX_XCORR_AMPLITUDE implements amplitude(ci, cq) on FPGA
* inlining the decoders in iso15693.c
* inlining memcpy/memset in LogTrace()
* giving up the moving correlator for SOF in Handle15693SamplesFromTag
* decode more of EOF in Handle15693SamplesFromTag()
* some refactoring
* added ISO15693 coding for tag messages (CodeIso15693AsTag())
* added ISO15693 decoding for reader commands (Handle15693SampleFromReader())
* send tag inventory response in either high or low speed
* some refactoring and formatting
* rework iso14443b device functions
* hf_read_rx_xcorr.v: transfer i/q pair in one 16bit frame
* hi_read_tx.v: invert ssp_dout. When nothing is transferred (ssp_dout=0), this results in no modulation (carrier on)
* adjust arm sources accordingly
* iso14443b.c: switch off carrier after hf 14b sri512read and hf 14b srix4kread
* iso14443b.c: fix DMA circular buffer handling
* FPGA Hi-Simulate: Formatted code
* FPGA Hi-Simulate: Fixed documantation
* FPGA Hi-Simulate: Freed up 4 LUTs
* FPGA Hi-Simulate: Added 212kHz SSP-Clock option
* Legic: Moved card simulator into separate file & cleaned interface.
Reader and card simulation have almost no common code. Moreover the sim
uses an SSP Clock at 212kHz for all timings to prevent any drifting from
the PRNG. This clock speed is not available in reader simulation mode (SSP
runs at up to 3.4MHz, and changes speed between TX and RX). For these
reasons having the code in separate files makes it significantly cleaner.
* Legic: Implemented RX and TX for card simulation
* Legic: Implemented setup phase for card simulation
* Legic: Implemented read command for card simulation
* Legic: Implemented write command for card simulation
* Legic: rewrite reader to use xcorrelation and precise timing
- Even tough Legic tags transmit just AM, receiving using
xcorrelation results in a significantly better signal
quality.
- Switching from bit bang to a hardware based ssc frees
up CPU time for other tasks e.g. prng and demodulation
- Having all times based on a fixed ts, results in perfect
rwd-tag synchronization without magic +/- calculations.
* hi_read_tx: remove jerry-riged hysteresis based receiver
- This feature got obsolete by a x-correlation based receiver.
* Legic: adjusted sampling to new ssp clock speed
- Sampling is 4 times faster and pipeline daly reduced to 1/4.
The new code samples each bit earyler to account for the
shorter pipeline. That introduced bit errors by leeking the
next bit into the current one.
* Legic: average 8 samples for better noise rejection.
* Update CHANGELOG.md
* ISO15693 device side improvements
* increase accuracy by doubling the sample frequency (hi_read_rx_xcorr.v)
* adjust armsrc/iso15693.c and client/cmdhf15.c accordingly
* use more accurate approximation for sqrt(ci^2 + cq^2)
* improve EOF detection (was often mistaken for Logic0, resulting in "error, uneven octet! (extra bits!)")
* hi_read_r_xcorr.v: avoid overflows during accumulation and truncation
* explicitely cast unsigned ADC samples to signed
* more timing fixes
* correctly determine correction bit (taken from iceman's fork)
* add checking of Access Conditions for Read command
* never allow reading KeyA
- fix: IQ demodulator (FPGA)
- fix: approximately align reader signal delay to tag response delay (FPGA)
- fix: remove deprecated RSSI calculation to improve decoder speed (iso14443b.c)
- fix: better approximation of signal amplitude to avoid false carrier detection (iso14443b.c)
- fix: remove initial power off in iso14443b raw command (iso14443b.c)
- add: enable tracing for iso14443b raw command (iso14443b.c)
- fix: client crashed when checking CRC for incomplete responses (iso14433b.c)
- speeding up snoop to avoid circular buffer overflow
- added some comments for better documentation
- rename functions (iso14443 -> iso14443b)
- remove unused code in hi_read_rx_xcorr.v
- most significant bit of tag data (which happens to be the sign bit)
had been dropped when snooping (FPGA change)
- avoid trying to decode both tag and reader data when snooping (we don't
have the time to do so).
This is a new LF edge detection algorithm for the FPGA.
- It uses a low-pass IIR filter to clean the signal
(see https://fail0verflow.com/blog/2014/proxmark3-fpga-iir-filter.html)
- The algorithm is able to detect consecutive peaks in the same
direction
- It uses an envelope follower to dynamically adjust the peak thresholds
- The main threshold used in the envelope follower can be set from the ARM side
fpga/lf_edge_detect.v,
fpga/lp20khz_1MSa_iir_filter.v,
fpga/min_max_tracker.v: New file.
fpga/lo_edge_detect.v, fpga/fpga_lf.v: Modify accordingly.
armsrc/apps.h (FPGA_CMD_SET_USER_BYTE1,
FPGA_CMD_SET_EDGE_DETECT_THRESHOLD): New FPGA command.
fpga/fpga_lf.v: Modify accordingly/Add a 8bit user register.
fpga/fpga_lf.bit: Update accordingly.
fpga/tests: New directory for testbenches
fpga/tests/Makefile: New file. It compiles the testbenches
and runs all the tests by default (comparing with the golden output)
fpga/tests/tb_lp20khz_1MSa_iir_filter.v,
fpga/tests/tb_min_max_tracker.v,
fpga/tests/tb_lf_edge_detect.v: New testbenches
fpga/tests/plot_edgedetect.py: New script to plot the results from
the edge detection tests.
fpga/tests/tb_data: New directory for data and golden outputs
- fixed a circular buffer rollover bug in iso14443a.c
- fixed 7 Byte UID handling in hf mf sniff
- fixed "cannot append" error in hf mf sniff d
- fixed hint on mfkey32 in hf mf sim x
- fixed hf mf sniff sometimes showing rogue data from previous calloc
- improve snooping/sniffing by syncing modulation detector window with reader signal (hi_iso14443a.v)
- code cleanup of hi_iso14443a.v
- enhanced tracing: hf 14a list now shows meaningful timing information. With new option f it also shows the frame delay times (fdt)
- small fix for hf 14b list - it used to run into the trace trailer
- hf 14a sim now obeys iso14443 timing (fdt of 1172 or 1234 resp.)
Note: you need to flash FPGA as well.
More details in http://www.proxmark.org/forum/viewtopic.php?pid=9721#p9721
