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Author SHA1 Message Date
Philippe Teuwen 2c41a61ee3 remove always true cond 2019-03-12 22:52:15 +01:00
Philippe Teuwen d50de828a1 flash write: check first page write 2019-03-12 22:50:29 +01:00
Philippe Teuwen 049f41a22f iso15693: fix strncat usage (one must specify available room, not total dest buffer size) 2019-03-12 21:55:36 +01:00
Philippe Teuwen cdf0a56fad iso15693: check memcpy and fix BuildInventoryResponse 
BuildInventoryResponse was copying 5 bytes instead of 12 bytes in the cmd buffer
 2019-03-12 21:55:36 +01:00
iceman1001 1d63258388 add: 'hf 14b raw' - added -t timeout option. see https://github.com/RfidResearchGroup/proxmark3/issues/125 2019-03-12 14:41:23 +01:00
iceman1001 35bc4a975e rename SNOOP -> SNIFF 2019-03-12 13:15:39 +01:00
Philippe Teuwen 1b2601a48a Add missing EOF LF 2019-03-12 00:12:26 +01:00
Philippe Teuwen 346af6e3d1 make style 2019-03-11 23:12:31 +01:00
iceman1001 ea53e1f981 clean up 2019-03-11 19:31:18 +01:00
iceman1001 780424fe11 chg: hitag2, some clean up, also testing to remove relay_off, since its never relay_on anywhere. 2019-03-11 14:56:03 +01:00
Philippe Teuwen 119e3f0ed9 Makefile: allow alternative platforms, try make PLATFORM=foo 2019-03-11 00:44:34 +01:00
iceman1001 b26e60dae9 turn off fpc default 2019-03-10 14:40:41 +01:00
iceman1001 40ccdb0e73 clean up 2019-03-10 14:39:46 +01:00
Philippe Teuwen 7d25c72e40 Makefile: recompile arm only when needed 2019-03-10 12:55:17 +01:00
Philippe Teuwen 2f12e57408 Makefiles: remove spurious spaces/tabs 2019-03-10 11:35:03 +01:00
Philippe Teuwen 961d929f4d changing {} style to match majority of previous style 2019-03-10 11:20:22 +01:00
Philippe Teuwen 0373696662 make style 2019-03-10 00:00:59 +01:00
Philippe Teuwen 8a7c6825b5 armsrc: fix mix of spaces & tabs 2019-03-09 20:34:41 +01:00
iceman1001 a819d522c1 textual 2019-03-09 11:51:46 +01:00
iceman1001 f4409ab375 chg: revert it 2019-03-09 11:51:18 +01:00
Philippe Teuwen 957464ca88 armsrc Standalone: fix mix of spaces & tabs 2019-03-09 11:19:45 +01:00
Philippe Teuwen 60f292b18e remove spurious spaces & tabs at end of lines 2019-03-09 08:59:13 +01:00
Philippe Teuwen edc19f202a Convert the few files with still Windows carriage returns 2019-03-09 08:49:41 +01:00
Philippe Teuwen 4160e32b0a Replace isNoise by computeSignalProperties and removeSignalOffset 2019-03-08 19:06:55 +01:00
Philippe Teuwen 4ffeebc193 Fix return code check for iso14443b_select_card in hf epa 2019-03-05 16:39:26 +01:00
vratiskol 99dc51e005 Mem Leak 2019-02-24 22:02:09 +01:00
iceman1001 4ea05fc026 Fix: 'hf mf fchk' - now reports back correct found keys. 2019-02-17 15:56:45 +01:00
iceman1001 7934630d2b FIX: Makefile bad styled calls 2019-02-14 19:27:39 +01:00
merlokk 69f3e65dd0 fix memmove if len=0 2019-02-05 18:39:03 +02:00
merlokk 0e5d896893 fix endless loop 2019-02-05 18:27:48 +02:00
bogiton 75aeec6507
Add led blink on successful flash write 2019-02-04 17:44:29 +00:00
merlokk cf21f046d8 arm side 2019-01-30 18:15:47 +02:00
merlokk 1b3d96ab2d add apdu chaining to arm side 2019-01-29 19:30:15 +02:00
iceman1001 8991fa172d FIX: wrong define 2019-01-29 15:47:44 +01:00
iceman1001 730a7e8044 FIX: 'hf legic sim' - needed even more timeout. 
see https://github.com/RfidResearchGroup/proxmark3/issues/83
 2019-01-25 13:48:53 +01:00
iceman1001 803aab7431 FIX: 'hf legic sim' - longer timeout for writes? (@drandreas) 
see https://github.com/RfidResearchGroup/proxmark3/issues/83
 2019-01-25 11:58:00 +01:00
iceman1001 0bec6038b7 CHG: adjusted compiling for older devices 2019-01-23 10:57:49 +01:00
iceman1001 20c3cd5ce3 chg: adjusting license according to earlier commits to pm3 offical repo. 2019-01-14 12:02:26 +01:00
iceman1001 a5833fe390 CHG: remove strange thr 0x43 in LF sampling 
CHG: refactor cotag init
 2019-01-12 12:10:31 +01:00
iceman1001 f215ebef80 Refactored 'lf t55xx brute', split it up into two commands. 
- lf t55xx brute  (tries bruteforcing a range of pwds
- lf t55xx chk    (uses dictionary file or RDV4 flashmem)

FIX: adjust lf sim (@marshmellow42)  see 7008cf9c15
"attempt to speed up the loops waiting for carrier signal to go high or low
by only checking for a halt (button press or usbpol) every 256th loop
iteration. some users were experiencing modulating reactions to be too slow.

ADD: 'lf t55xx chk'
It uses @marshmellows42 idea behind commit  (6178b085a0)
With calculating a baseline (read block0 32times and average the signal-ish) and sampling only 1024 signal data. The algo then proceeds to calc the average and keep track of the candidate which is given the most difference in signal data average value.    I do some squaring and shifting for this.
The candidate is then send back to client to be tested properly with  trymodulation like before.

This seems to work good on t55xx card which has a ASK configuration.

WORK-IN-PROGRESS
 2019-01-11 14:46:27 +01:00
iceman1001 8a514ea8f1 REM: remove unused files 2019-01-09 16:28:06 +01:00
iceman1001 e276bf1ce3 FIX: gcc8.1 warnings 2019-01-09 16:25:49 +01:00
iceman1001 6743e45386 CHG: name changes 2019-01-09 12:05:29 +01:00
iceman1001 2612cd006a CHG: bigbuf adaptations 2019-01-09 12:00:06 +01:00
iceman1001 3ae871f534 CHG: 'hf 14a antifuzz' - original implementation by @asfabw, reworked a bit - WORK IN PROGRESS - 2019-01-07 09:32:16 +01:00
iceman1001 c1237cfa26 FIX: 'lg pcf7931' - improved read code (@sguerrini97) 2019-01-06 21:05:29 +01:00
iceman1001 c37cc81c00 CHG: FeliCa more details 2019-01-06 20:42:51 +01:00
iceman1001 0dee369a58 FIX: 'hf tune' - now works... 2019-01-06 20:28:23 +01:00
iceman1001 38853b111f FIX: adding directives to reduce size on systems like Gentoo Hardned (see https://github.com/iceman1001/proxmark3/issues/268) 2019-01-05 20:59:00 +01:00
iceman1001 6e281a08ed CHG: 'hf mf fchk' - speed improvments by tweaking implementation. 
CHG: 'hf mf fchk' - can use dictionary from flashmem if one is uploaded. (faster)
 2019-01-02 11:52:13 +01:00
iceman1001 0fb0c35308 CHG: 'mem load' - the possibility to upload default_iclass_keys.dic, default_keys.dic, default_pwd.dic to predefined flashmemory sections. These will be used in pwd / key checking algorithms on device. 
CHG: 'script run read_pwd_mem.lua' - script now can print those uploaded dictionary files.

How to upload
pm3 --> mem load f default_iclass_keys i
pm3 --> mem load f default_keys m
pm3 --> mem load f default_pwd t

How to validate / view
PM3 -->scr run read_pwd_mem -o 237568 -k 8
pm3 -->scr run read_pwd_mem -o 241664 -k 6
pm3 -->scr run read_pwd_mem -o 245760 -k 4
 2019-01-01 18:01:40 +01:00
Chris f8c33af1da CHG: FPC connector tests. Device -> Client communications works. 
Adjust  armsrc/Makefile   and client/Makefile  to include  the  -DWITH_FPC  flag to compile with FPC enabled.
 2018-11-20 10:58:32 +01:00
Chris aa3b322d0f chg: 'analyze a' - some fpc test changes. 2018-11-16 23:59:14 +01:00
Chris faef1a0938 chg: lf simulation - trying the new clock for better timings. 2018-11-16 23:57:55 +01:00
Chris fd1c0cac79 FIX: 'standalone mode MattyRun' - compiles and should even work 
CHG: 'standalone mode' - generic banner for each mode. Updated the ledshow to @cjbrigato
 2018-11-16 02:52:42 +01:00
Chris 9bff2ab74f CHG: cleaning up 2018-11-14 15:06:28 +01:00
Chris bac3ad077e FIX: 'standalone mode colinrun' - buffer overrun (thanks @angelsl) 
1aa974fc70
 2018-11-14 09:05:08 +01:00
merlokk 1f1d8bfc0b fixed armside epa.c 2018-11-08 20:29:29 +02:00
merlokk 0cfa47e628 merged iso14 arm side 2018-11-08 20:29:08 +02:00
RFID Research Group ce30c29f47
Merge branch 'master' into master 2018-11-07 12:12:47 +01:00
Chris 078196773c CHG: 'standalone bogitorun' - adapted some ledshow from Kigiv mode and increased time for user to stop pressing button after triggering the mode.. 2018-11-06 22:20:55 +01:00
Chris 5a03ea7135 chg: 'standalone mode BogRun' - cleaning 2018-11-06 19:14:19 +01:00
Chris 4d124c46f2 chg: 'standlone mode colinrun aka KIGIV' - made it smaller to fit a normal compilation of fullimage 2018-11-06 19:13:06 +01:00
bogiton d6d96eb7fe
Fixed offset bug (thanks iceman) 2018-11-06 13:36:00 +00:00
Chris 98e24013cf chg: 'hf mf chk' - since the function ends with droping the field, lets just make sure the field is off to start with. 2018-11-05 22:34:46 +01:00
Chris 4da4b33d8d fix: 'lf t55xx deviceconfig' - bug that failed to load default values if wiped flashmem. 2018-11-01 19:51:45 +01:00
RFID Research Group 8759c0a9f7
Merge pull request #44 from bogiton/master 
Standalone HF Sniff (and ULC/NTAG/ULEV1 pwd storing)
 2018-10-28 15:31:50 +01:00
bogiton 2718e783dc
Added small description 2018-10-28 13:54:38 +00:00
bogiton 43f90181b3
Update hf_bog.c 2018-10-28 13:34:42 +00:00
bogiton 9bd7770dfe
Revert to default standalone mode 2018-10-28 12:04:44 +00:00
bogiton 785ab8f73e
Baudrate and optimization (removed counter) 2018-10-28 12:01:36 +00:00
bogiton 34775c81f5
Added BogitoRun identification 2018-10-21 18:29:49 +00:00
Chris 22fb92f9c8 sugar 2018-10-21 19:51:22 +02:00
bogiton 1c2af2a5ed
Added hf_bog standalone 2018-10-16 19:50:18 +00:00
bogiton 8079613b37
Add check for the HF_BOG directive for RunMod 2018-10-16 19:41:05 +00:00
bogiton 34c1da7ad4
Include the HF_BOG standalone mode 2018-10-16 19:39:29 +00:00
Chris dc67b5d7c9 chg: revert fpga_major mode in LF. 
chg: 'lf t55xx deviceconfig'  - persistence to flashmem is now option with param P
 2018-09-23 05:29:55 +02:00
Chris d596343438 chg: 'lf t55xx deviceconfig' - assume total time, and writeenable when writting... 2018-09-16 20:48:39 +02:00
Chris 02cc278e19 chg: remove warnings on coverity 
chg: encapsule flasmem function calls
 2018-09-16 20:47:23 +02:00
TomHarkness 3e9397e337 Fix syntax 2018-09-15 16:20:44 +10:00
Chris 43c399876f chg: helptext 2018-09-12 07:59:43 +02:00
Chris ba2543b627 ADD: 'lf t55xx deviceconfig' - command that allows for setting t55xx timings via the client. If run on a RDV40, it also saves the config to flashmemory. This gives you option to have custom timings for your custom antenna in order for your RDV40 to work optimal against a t55xx tag and with your custom antenna. (@iceman) 2018-09-11 18:35:07 +02:00
Chris 9ee550af45 FIX: lf t55xx detect works better with adjusted timings 
CHG: applied fpga_off patch.
 2018-09-10 21:45:00 +02:00
Chris 90f29bf430 chg: call specific noise function 2018-09-09 11:29:37 +02:00
Chris ba9de80eeb chg: 'hf legic sim' break sim by sending another cmd 2018-09-09 11:29:11 +02:00
Chris 79afc031fc FIX: LF antenna discharge after interfer timings. As suggested by @ts And thanks to @drandreas who patiently explains fpga verilog code to me. 
This introduces a new majoe mode, FPGA_MAJOR_MODE_OFF_LF,  which should ONLY be used in sending loops for LF.   Basically the PWR_LO is set HIGH in order to discharge voltage faster.

Once sending is over,  the normal FPGA_MAJOR_MODE_OFF SHALL be used.
 2018-09-08 14:11:51 +02:00
Chris e5e8c0b5d8 not needed anymore 2018-09-07 23:45:08 +02:00
Chris 24eaac8681 CHG: the thread comms refactoring from offical pm3 repo 
chg: FPC com speed limited to 115200 when compiled with FPC
chg: USART remake (@drandreas)
 2018-09-06 21:43:20 +02:00
RFID Research Group eb0b5116a2
Merge pull request #25 from drandreas/rdv4-legic 
Legic Tag Simulator
 2018-09-06 20:26:39 +02:00
Colin J. Brigato 7e12fc0ceb Pass 2; commit 3/3; 2018-09-06 05:34:48 +02:00
Colin J. Brigato 368fe11df0 Second Pass rewrite of flashmem. added command 'mem spibaud' to switch between 24/48Mhz operation. All is more consistant, less messy. All logic rewrittent avoiding multiple flashinit/flashstop. busywait is now at it's lowest possible. Beware : 48Mhz is VERY buggy cause of sillicon bug (see source for more info), and doesn't give much more than 24Mhz for now since we doubled nearly every operation speed here. 2018-09-06 05:15:52 +02:00
AntiCat e1fa1e659a Legic: Implemented write command for card simulation 2018-09-05 23:03:05 +02:00
AntiCat 2981fe7ce8 Legic: Implemented read command for card simulation 2018-09-05 23:03:05 +02:00
AntiCat cd78b00815 Legic: Implemented setup phase for card simulation 2018-09-05 23:03:05 +02:00
AntiCat 2c6c4e5bc6 Legic: Implemented trace log 2018-09-05 23:03:05 +02:00
AntiCat fe91a3f52f Legic: Implemented RX and TX for card simulation 2018-09-05 23:03:05 +02:00
AntiCat 61e4eac2b2 Legic: Moved card simulator into separate file & cleaned interface. 
Reader and card simulation have almost no common code. Moreover the sim
uses an SSP Clock at 212kHz for all timings to prevent any drifting from
the PRNG. This clock speed is not available in reader simulation mode (SSP
runs at up to 3.4MHz, and changes speed between TX and RX). For these
reasons having the code in separate files makes it significantly cleaner.
 2018-09-05 23:03:04 +02:00
Colin J. Brigato 76e2d7502a Merge remote-tracking branch 'upstream/master' 2018-09-05 20:39:56 +02:00
Colin J. Brigato 2263c826db Restore Makefile, temporiraly provide Makefile.Colin 2018-09-05 20:34:28 +02:00
Chris 4c72acaf63 FIX: cleanup code, sync of output texts. 2018-09-05 18:58:58 +02:00
Chris 4c37126baf cleanup 2018-09-05 18:58:04 +02:00
def b7bdc69e5a lfops.c CmdEM410xdemod empty TAG ID fix. 2018-09-05 17:50:31 +03:00
Chris 307063474d CHG: cleanup 2018-09-04 20:36:25 +02:00
Chris ac6bd61544 FIX: longer t55xx timings to compensate for delay of field damping, and minor adjustments. 2018-09-04 20:35:29 +02:00
Chris e12d22b6d9 FIX: 'LF Standalone modes' - Ensure that noise check is performed for any device-side processing otherwise device-side processing will see all LF signals as noise. 
From: 8bddce8096
 2018-09-04 20:32:52 +02:00
Chris 27a036b087 FIX: logic behind compiler directive is now correct 2018-09-04 20:31:12 +02:00
Iceman 701b96d7fe
Update readme.md 2018-09-03 22:45:01 +02:00
Chris 76e7603ef1 textual 2018-09-03 22:36:43 +02:00
Chris 0e3ba1c058 CHG: easier to configure compilation of standalone mode. Just swap -D directive once your new standalone mode is ready and you added your code for it 
based on a modification by @marshmellow42
 2018-09-03 22:27:18 +02:00
Colin J. Brigato 8d673fa1bf First pass rewrite of flashmem driver for optimization. Lot of changes here. Provides PoC of saving and recalling a tag in Standalone mode. Added some printing passthrough to client to azccomodate for vt100 eye-candyness. FastREAD mode implemented for flashmem, testable from client. Beta but functionnal. Reading the whole flash with 1Kb to 32kb buffers was ~730ms, now 380ms Max (even at 24Mhz spi baudrate) 2018-09-03 00:02:44 +02:00
Chris f1d0e9db4d fix: revert back 2018-08-29 19:42:46 +02:00
Chris 42e883f67b FIX: print_result - now prints correct len. 
FIX: DOWNLOAD_BUFFER -  now with correct result logic
 2018-08-28 21:15:28 +02:00
Chris ca5b476730 FIX: 'standanlonemode colin' - mifare1ksim called with correct params (@cjbrigato) 2018-08-26 08:19:59 +02:00
Chris 2eab02e3ba CHG: 'standalone mode MattyRun' - added some comments and suggestion 2018-08-25 23:26:04 +02:00
Chris fe332a1f2b removed unneeded ramfunc attribute 2018-08-13 23:50:17 +02:00
Chris 91dea8d694 code clean. 2018-08-13 23:49:33 +02:00
Chris 5f77121694 initial commit to be in sync the-soon-defunct repo pm3rdv40. 2018-08-12 21:54:31 +02:00
Andreas Dröscher 9ba20b590a change: reduced demodulator to bare minimum 
The initial code added complexity without improving reading distance.
Thankfully the peak detection signal path has a low noise floor.
 2018-08-12 12:51:45 +02:00
Andreas Dröscher 0d0b651246 change: re-added trace log 2018-08-12 12:51:45 +02:00
Andreas Dröscher ff5b046903 change: re-added status LEDs 
- LED_A: FPGA and 13.56MHz carrier is active
- LED_B: Reading Byte
- LED_C: Writing Byte
 2018-08-12 12:41:45 +02:00
Andreas Dröscher e052fbc433 change: re-added legic write support 2018-08-12 12:41:45 +02:00
Andreas Dröscher 9d330dde87 fix: 32bit tick timer based on TC0 and TC1 
TC1 counts the number of TC0 overflows (carry bits).
In random conditions TC1 would return or stay at zero,
instead of counting up. This due to the behavior of the
reset signal.

SAM7S Series Datasheet, 33.5.6 Trigger:
Regardless of the trigger used, it will be taken into account
at the following active edge of the selected clock. This means
that the counter value can be read differently from zero just
after a trigger, especially when a low frequency signal is
selected as the clock.

The new code first prepares TC1 and asserts TC1 trigger and
then prepares TC0 and asserts TC0 trigger. The TC0 start-up
will reset TC1.
 2018-08-12 12:41:11 +02:00
Andreas Dröscher c06f0af7f3 change: switched from timestamps (us) to ticks 
GetCountUS() has a jitter of +/- 7us this is not precise
enough to keep the PRNG in sync. 1.5 * GET_TICKS on the
other hand is spot on.
 2018-08-12 09:59:48 +02:00
Andreas Dröscher e0adc976e0 change: added rx/tx coordination timestamp 2018-08-12 09:59:48 +02:00
Andreas Dröscher 7244f5825d change: legic reader tx back to bigbang 
I've tried to modulate the Legic specific pause-puls using ssc and the default
ssc clock of 105.4 kHz (bit periode of 9.4us) - previous commit. However,
the timing was not precise enough. By increasing the ssc clock this could
be circumvented, but the adventage over bitbang would be little.
 2018-08-12 09:59:48 +02:00
Andreas Dröscher 3029223158 change: legic reader now uses xcorrelation and ssc based io 
- Even tough legic tags transmit just AM using xcorrelation
   results in a significantly better signal quality.
 - Switching from bit bang to a hardware based ssc frees
   up CPU time for other tasks e.g. demodulation
 2018-08-12 09:59:48 +02:00
Andreas Dröscher c59150657c add: xcorr 211.875 kHz option 
The FPGA supported this frequency for a long time, just the ARM code
had no define to enable it.
 2018-08-12 09:59:48 +02:00
Andreas Dröscher db70ab8f7d change: remove broken legic simulator 
It will be rewritten in a later commit
 2018-08-12 09:59:48 +02:00
Andreas Dröscher 8a53137ab0 change: remove dead legic code 
This code was either disabled or never reached.
 2018-08-12 09:59:48 +02:00
Andreas Dröscher e779f06c5e change: clean up Legic interface 
I see no adventage in poluting all sources that include legicrf.h
with our internal depedencies (includes) and function names.
 2018-08-12 09:59:48 +02:00
Iceman c339035ec5
Revert "WIP: Clean Legic Reader" 2018-08-06 15:05:36 +02:00
Andreas Dröscher 058426fa17 change: added rx/tx coordination timestamp 2018-08-05 00:57:20 +02:00
Andreas Dröscher 8f797d1388 change: legic reader tx back to bigbang 
I've tried to modulate the Legic specific pause-puls using ssc and the default
ssc clock of 105.4 kHz (bit periode of 9.4us) - previous commit. However,
the timing was not precise enough. By increasing the ssc clock this could
be circumvented, but the adventage over bitbang would be little.
 2018-08-05 00:57:20 +02:00
Andreas Dröscher 78d5188922 change: legic reader now uses xcorrelation and ssc based io 
- Even tough legic tags transmit just AM using xcorrelation
   results in a significantly better signal quality.
 - Switching from bit bang to a hardware based ssc frees
   up CPU time for other tasks e.g. demodulation
 2018-08-04 23:13:17 +02:00
Andreas Dröscher d7c57dbc08 add: xcorr 211.875 kHz option 
The FPGA supported this frequency for a long time, just the ARM code
had no define to enable it.
 2018-08-04 23:13:17 +02:00
Andreas Dröscher 1adff322b1 change: remove broken legic simulator 
It will be rewritten in a later commit
 2018-08-04 23:13:17 +02:00
Andreas Dröscher 33eb2f5fa0 change: remove dead legic code 
This code was either disabled or never reached.
 2018-08-04 23:13:17 +02:00
Andreas Dröscher 37867fbf3b change: clean up Legic interface 
I see no adventage in poluting all sources that include legicrf.h
with our internal depedencies (includes) and function names.
 2018-08-04 23:13:17 +02:00
Chris bacf8aff0f add: FPC connector skeleton usart. Not working but if will be a starting point for those who might want to help out with it. 2018-07-30 09:54:44 +02:00
iceman1001 08d9d9daf9 cleaning 2018-07-29 18:20:56 +02:00
iceman1001 c082531110 fix: potential implicit type cast issue (Thanks to @drandreas for pointing it out) 2018-07-29 18:20:39 +02:00
iceman1001 506da3ff4c textual 2018-07-29 16:30:36 +02:00
iceman1001 4172ea6c19 cleanup 2018-07-28 14:26:37 +02:00
iceman1001 4d8488e14b CHG: https://github.com/Proxmark/proxmark3/pull/631 from offical repo. (piwi) 
CHG: textual adjustments
 2018-07-28 14:25:12 +02:00
Chris afeb0d0cd7 fix: removes unneeded floating point lib inclusion (@piwi) 2018-07-23 21:02:13 +02:00
Chris fff2f51cfb chg: testing to switch from WaitXX calls to SpinDelay, they seem to mess up 2018-07-06 09:10:13 +02:00
Chris 79158c7360 chg; preparing for more cmds. 2018-07-06 00:24:04 +02:00
Chris 36d774506c chg: 'sm raw' - implemented 'r' don't read reply 2018-07-05 21:10:21 +02:00
Chris 2ccbde8110 chg: 'flashmem' - adjust debugstatemnts 2018-07-05 20:29:16 +02:00
Chris fca841122f chg: 'sc reader' - hooked up atr. 2018-07-05 16:32:10 +02:00