Commit graph

119 commits

Author SHA1 Message Date
AntiCat
e472a21194 FPGA Hi-Simulate: Added 212kHz SSP-Clock option 2018-09-05 23:01:55 +02:00
AntiCat
0994c91888 FPGA Hi-Simulate: Freed up 4 LUTs 2018-09-05 23:01:55 +02:00
AntiCat
cef5dc4e83 FPGA Hi-Simulate: Fixed documantation 2018-09-05 23:01:55 +02:00
AntiCat
6ca899d130 FPGA Hi-Simulate: Formatted code 2018-09-05 23:01:55 +02:00
Andreas Dröscher
bf123082e8 change: remove jerry-riged hysteresis based receiver from hi_read_tx
This future got obsolete by a x-correlation based receiver.

This reverts commit 24fe4dffb4.
2018-08-12 09:59:48 +02:00
Andreas Dröscher
83a4259ddc change: fixed xcorrelation for strong signal
The initial code assumed phase shift modulation only. Lately,
xcorrelation is also used for load modulation. But the initial
the assumption that 11 bits are enough isn't true for load
modulation.

This change extends the registers by 2 bits and compresses the
uper bits to preserve the sensitivity on the lower end.
2018-08-10 02:36:04 +02:00
Iceman
c339035ec5
Revert "WIP: Clean Legic Reader" 2018-08-06 15:05:36 +02:00
Andreas Dröscher
78d5188922 change: legic reader now uses xcorrelation and ssc based io
- Even tough legic tags transmit just AM using xcorrelation
   results in a significantly better signal quality.
 - Switching from bit bang to a hardware based ssc frees
   up CPU time for other tasks e.g. demodulation
2018-08-04 23:13:17 +02:00
Andreas Dröscher
7517c894d2 change: remove jerry-riged hysteresis based receiver from hi_read_tx
This future got obsolete by a x-correlation based receiver.

This reverts commit 24fe4dffb4.
2018-08-04 23:13:17 +02:00
iceman1001
84b7ea82bb fix: legic functionality for RDV40. Getting 2-3cm reading distances now. 2018-07-28 18:45:13 +02:00
iceman1001
ccfcd8e991 CHG: Thanks to @pwpiwi , his latest adjustments to HF. 2017-11-10 19:51:37 +01:00
iceman1001
994248265d FIX: changing the result booleran when sending over serial. 2017-10-29 19:22:03 +01:00
iceman1001
1a7badc025 REM: removed unused file 2017-10-25 14:12:29 +02:00
iceman1001
3fd792940b FIX: @satsuoni fixes with pm3 offical version. 2017-10-25 13:59:49 +02:00
iceman1001
c2444a885b CHG: FeliCa and 14b/15 enhancements. or it should be atleast. Until it gets tested.. 2017-10-24 18:24:30 +02:00
iceman1001
8f201fd173 chg: removed some commented out code 2017-10-23 22:10:16 +02:00
iceman1001
f3ebfcb9a0 chg: reverting old @satsuoni felica changes.
chg: applied @pwpiwi 's fixes for iso 14B / 15
2017-10-23 21:56:47 +02:00
iceman1001
74ac547db8 REM: removed unused file 2017-10-20 20:29:38 +02:00
iceman1001
4b63f940f1 CHG: FeliCa implemenation by @satsuoni 2017-10-20 20:27:44 +02:00
iceman1001
11f975c37e ADD: FPGA FeliCa binary file aswell.. Thanks to @Satsuoni 2017-10-10 14:07:30 +02:00
iceman1001
7af5e29e22 ADD: FPGA missing file Thanks to @Satsuoni 2017-10-10 14:03:09 +02:00
iceman1001
5c1f7686f6 ADD: FPGA code to support FeliCa / ISO 18092. Thanks to @satsuoni 2017-10-10 14:01:58 +02:00
iceman1001
8bc17414fd new coverity scan complains..
fix 'lf hitag'  bit comparisions wrong
fix 'standalone mode'  logically dead code
2017-07-07 15:45:40 +02:00
iceman1001
1ef14f2d9d fix: the updated fpga_hf.bit file, where iso15693 should work. 2017-07-07 09:20:23 +02:00
iceman1001
07bc72b880 CHG: continue code cleanup.
REM: removed stdint.h ,  since we are using c99 when compiling.
2017-02-23 00:32:14 +01:00
iceman1001
496b673453 Added some comments 2017-01-26 14:23:48 +01:00
iceman1001
eb7eab8570 code cleanup. 2016-03-20 19:33:59 +01:00
iceman1001
ef8e50c64b CHG: has the order of varibles some impact? I re-arranged them to match. 2016-03-13 07:18:04 +01:00
iceman1001
f5d2e7f7df CHG: @ematrix / @piwi fixes for 'hf snoop' 2015-11-02 11:41:25 +01:00
iceman1001
afa86e5c03 ADD: help text for 'hf snoop' / 'hf search' / 'hf list'
CHG: minor code changes.
CHG: makefile ,  moved hi_sniffer.v from LF into HF row.  @piwi suggestion for PR https://github.com/Proxmark/proxmark3/pull/141
2015-11-01 19:49:08 +01:00
iceman1001
eb4222d773 CHG: the updated fpga image for the "hf snoop" 2015-10-30 09:10:09 +01:00
iceman1001
1d0ccbe04b ADD: added the "hf snoop" patch original from @Enio, rearranged by @Etmatrix.
ADD:  added the "t55x7" refactoring by @marshmellow42
2015-10-27 21:47:21 +01:00
pwpiwi
705bfa1058 fixing iso14443b (issue #103):
- increased DMA_BUFFER_SIZE to avoid occasional circular buffer overflows.
- minor code cleanups
2015-06-22 22:03:43 +02:00
pwpiwi
467340996e fixing iso14443b (issue #103):
- fix hf 14b snoop
- fix hf 14b sim
2015-06-21 18:04:24 +02:00
pwpiwi
da586b1702 fixing iso14443b (issue #103):
- revert removal of FPGA_HF_READER_RX_XCORR_848_KHZ. Need to be able to switch to 424kHz for ISO15693.
2015-06-18 15:41:30 +02:00
pwpiwi
51d4f6f114 fixing iso14443b (issue #103):
- fix: IQ demodulator (FPGA)
- fix: approximately align reader signal delay to tag response delay (FPGA)
- fix: remove deprecated RSSI calculation to improve decoder speed (iso14443b.c)
- fix: better approximation of signal amplitude to avoid false carrier detection (iso14443b.c)
- fix: remove initial power off in iso14443b raw command (iso14443b.c)
- add: enable tracing for iso14443b raw command (iso14443b.c)
- fix: client crashed when checking CRC for incomplete responses (iso14433b.c)
- speeding up snoop to avoid circular buffer overflow
- added some comments for better documentation
- rename functions (iso14443 -> iso14443b)
- remove unused code in hi_read_rx_xcorr.v
2015-06-17 20:27:36 +02:00
pwpiwi
09c66f1f09 fixing iso14443b (issue #103): fix timing issue (speeding up
the decoders)
2015-06-03 13:28:28 +02:00
pwpiwi
5b95953d42 fixing iso14443b (issue #103):
- most significant bit of tag data (which happens to be the sign bit)
had been dropped when snooping (FPGA change)
- avoid trying to decode both tag and reader data when snooping (we don't
have the time to do so).
2015-06-02 22:50:16 +02:00
pwpiwi
30364d2711 fix: broken edge detector implementation in hi_iso14443a.v resulted in decreased sensitivity 2015-03-09 20:01:37 +01:00
pwpiwi
7843130a58 fix: (issue #72) LF simulation didn't work with lo_edge_detect.v 2015-03-06 07:42:54 +01:00
pwpiwi
7554370c30 bugfix hf 14a sim / hf mf sim: polarity of tag subcarrier modulation was wrong 2015-02-11 21:14:34 +01:00
Martin Holst Swende
09b69422e2 This was resynthezised along with my hf-changes. Nothing changed though 2015-01-15 15:29:03 +01:00
Martin Holst Swende
645c960f61 Implemented new FPGA mode for iclass tag simulation. Reduces arm-side size of transfer/memory by a factor of 8. Makes for easier arm-side encoding of messages, for when we start needing to do that on the fly instead of using precalculated messages 2015-01-15 15:16:34 +01:00
iZsh
238c503c38 fpga/min_max_tracker.v: english 2014-06-27 23:28:56 +02:00
iZsh
3b2fee43ea New LF edge detection algorithm + lowpass filter
This is a new LF edge detection algorithm for the FPGA.

- It uses a low-pass IIR filter to clean the signal
(see https://fail0verflow.com/blog/2014/proxmark3-fpga-iir-filter.html)
- The algorithm is able to detect consecutive peaks in the same
  direction
- It uses an envelope follower to dynamically adjust the peak thresholds
- The main threshold used in the envelope follower can be set from the ARM side

fpga/lf_edge_detect.v,
fpga/lp20khz_1MSa_iir_filter.v,
fpga/min_max_tracker.v: New file.

fpga/lo_edge_detect.v, fpga/fpga_lf.v: Modify accordingly.

armsrc/apps.h (FPGA_CMD_SET_USER_BYTE1,
FPGA_CMD_SET_EDGE_DETECT_THRESHOLD): New FPGA command.
fpga/fpga_lf.v: Modify accordingly/Add a 8bit user register.

fpga/fpga_lf.bit: Update accordingly.

fpga/tests: New directory for testbenches

fpga/tests/Makefile: New file. It compiles the testbenches
and runs all the tests by default (comparing with the golden output)

fpga/tests/tb_lp20khz_1MSa_iir_filter.v,
fpga/tests/tb_min_max_tracker.v,
fpga/tests/tb_lf_edge_detect.v: New testbenches

fpga/tests/plot_edgedetect.py: New script to plot the results from
the edge detection tests.

fpga/tests/tb_data: New directory for data and golden outputs
2014-06-27 14:27:03 +02:00
iZsh
b014c96d68 new command "lf snoop" to snoop raw ADC values
fpga/lo_read.v (lf_field): new argument.
fpga/fpga_lf.v: modify accordingly.

armsrc/apps.h (FPGA_MAJOR_MODE_LF_READER): Rename as FPGA_MAJOR_MODE_LF_ADC.
armsrc/apps.h (FPGA_LF_ADC_READER_FIELD): New LF option.
armsrc/lfops.c: Modify accordingly.

client/cmdlf.c (CmdLFSnoop): New command.
armsrc/appmain.c, armsrc/lfops.c, client/cmdlf.h, include/usb_cmd.h: Modify accordingly.
2014-06-21 21:33:54 +02:00
iZsh
fa57f6e12e fpga/fpga_hf.v, fpga_lf.v, lo_edge_detect.v, lo_passthru.v, lo_read.v: copyright notice 2014-06-20 12:38:58 +02:00
iZsh
7cc204bff8 THIS REQUIRES A BOOTROM UPDATE!! To save FPGA area, split the LF and HF bitstreams and load them on-demand. 2014-06-20 01:02:59 +02:00
Martin Holst Swende
94090295a7 new fpga image for better iso15693 simulation 2014-06-07 21:44:45 +02:00
Martin Holst Swende
12401d8dbc Added 424KHz mode for iso 15693 simulation 2014-06-07 21:39:52 +02:00
pwpiwi
d714d3effc Improvements/Fixes to 14443 sniffing/snooping
- fixed a circular buffer rollover bug in iso14443a.c
- fixed 7 Byte UID handling in hf mf sniff
- fixed "cannot append" error in hf mf sniff d
- fixed hint on mfkey32 in hf mf sim x
- fixed hf mf sniff sometimes showing rogue data from previous calloc
- improve snooping/sniffing by syncing modulation detector window with reader signal (hi_iso14443a.v)
- code cleanup of hi_iso14443a.v
2014-03-25 21:38:24 +01:00
micki.held@gmx.de
552cbc5890 iso14444a: minor FPGA bugfix 2014-02-25 06:49:49 +00:00
micki.held@gmx.de
d7aa3739a9 More robust iso14443a sniffing/simulation functions by
- iso14443a.c: less strict Miller/Manchester decoders
- FPGA hi_iso14443a.v: syncing on external readers' clock when simulating and sniffing.
2014-02-23 15:46:19 +00:00
micki.held@gmx.de
7bc95e2e43 - fixed iso1443a ManchesterDecoder in order to fix broken Snoop/Sniff
- enhanced tracing: hf 14a list now shows meaningful timing information. With new option f it also shows the frame delay times (fdt)
- small fix for hf 14b list - it used to run into the trace trailer
- hf 14a sim now obeys iso14443 timing (fdt of 1172 or 1234 resp.)
Note: you need to flash FPGA as well.
More details in http://www.proxmark.org/forum/viewtopic.php?pid=9721#p9721
2014-02-19 20:35:04 +00:00
micki.held@gmx.de
e691fc45bc - improved reader sensitivity for 14443a cards (FPGA change!)
- implemented ISO 14443A anticollision loop
See http://www.proxmark.org/forum/viewtopic.php?id=1797 further details
2013-11-19 18:52:40 +00:00
roel@libnfc.org
d19929cbe8 MAJOR update, added hitag2 reader, emulation and eavesdropping, lots of new code, including FPGA tweaks, part 2 2012-09-18 13:53:17 +00:00
bushing
ba06a4b694 setting svn:eol-style=native on files, part 3
(should be done now, sorry)
2010-02-22 19:29:05 +00:00
henryk@ploetzli.ch
8d40aba58b Add capability to correlate against subcarriers of 212kHz (argument FPGA_HF_READER_RX_XCORR_QUARTER_FREQ | FPGA_HF_READER_RX_XCORR_848_KHZ) and 106kHz (argument FPGA_HF_READER_RX_XCORR_QUARTER_FREQ) 2009-12-09 02:31:01 +00:00
henryk@ploetzli.ch
24fe4dffb4 Jerry-rig a simply hysteresis based receiver into hi_read_tx. Output is via SSC_DIN, which wasn't used in that mode before. 2009-11-06 15:36:57 +00:00
henryk@ploetzli.ch
ecf53cb215 Add HF simulator modulation mode for 212kHz subcarrier 2009-10-12 07:46:03 +00:00
henryk@ploetzli.ch
db335b3de0 Make objcopy call less verbose
Add master Makefile
2009-08-30 22:35:12 +00:00
henryk@ploetzli.ch
802a36162a New FPGA code for bidirectional LF emulation 2009-08-28 21:54:47 +00:00
henryk@ploetzli.ch
e73e717239 Add Makefile for fpga directory (Windows codepath is untested, in any case, go.bat is still there)
Retire rbt2c.pl, instead use objcopy to directly convert the .bit file into an .o that can be linked with the flash image
Rename armsrc/fpga.c to armsrc/fpgaloader.c (since there is now a new fpga.o, created from fpga.bit)
Remove fpgaimg.c from subversion, add fpga.bit
Instead of creating fpgaimage.elf and osimage.elf separately, now create a joined fullimage.elf 
  first (obsoleting ldscript-full), then extract only the fpga and os sections with objcopy
  (This creates unspecific warnings about an empty segment, need to investigate)
Implement a rudimentary .bit parser in the firmware, use that to locate the bitstream in the new
  fpgaimage (which is just a plain copy of the fpga.bit file) and send it to the FPGA
  The code will check the format that's in flash and fall back to the legacy format
2009-08-27 23:29:49 +00:00
d18c7db
8e7a6ce409 This version code now reads a TI tag properly. 2009-07-20 10:36:33 +00:00
d18c7db
4a2d037658 Rubbish file leftover from FPGA compile. Not source code. 2009-07-19 03:52:18 +00:00
d18c7db
72acba7884 Added FPGA passthrough mode for TI tags 2009-07-19 03:51:06 +00:00
d18c7db
1c38843b3f Updated logic in lo_read.v so it's much tidier now, better timing.
Commented source and recompiled FPGA to new fpgaimg.c
2009-04-16 23:09:21 +00:00
edouard@lafargue.name
30f2a7d38f Added LF frequency adjustments from d18c7db, cleaned up code,
typo fixes in iso14443a code, added the missing "tools" directory,
added initial elements for online/offline detection for commands.
2009-04-15 08:09:06 +00:00
edouard@lafargue.name
6658905f18 Initial commit for the firmware. Used the 20090306_ela version as baseline.
It is identical to the popular 20081211, with the doob addition (20090301), a
linux client, and two additional commands for LF analysis. Let me know if
you find issues here!
2009-04-09 06:43:20 +00:00