Commit graph

116 commits

Author SHA1 Message Date
iceman1001 0be35a8e7e style 2020-09-07 10:35:09 +02:00
iceman1001 ae7fc5006e mergehell, piwi's legic changes 2020-09-06 20:06:24 +02:00
iceman1001 837efdf5c4 chg: adapt to fpga changes 2020-07-02 12:36:24 +02:00
iceman1001 47634f5550 change: remove inline directive in armsrc, since we are optimizing for size 2020-05-19 17:15:07 +02:00
Philippe Teuwen fbaf634779 legicrf & gcc 10: Remove inline warning 2020-05-19 16:34:00 +02:00
iceman1001 8f188a5329 redundant 2020-05-12 10:27:54 +02:00
Philippe Teuwen 026707b960 arm: fix prototypes 2020-05-11 13:48:57 +02:00
Philippe Teuwen 838d345918 resolve inline warnings 2020-05-11 13:48:57 +02:00
Philippe Teuwen 94192d0976 make style 2020-04-16 09:01:14 +02:00
iceman1001 a42a817ff3 MIX, also removeed returning mem, since its not used. We use downloadEMbuffer instead 2020-04-08 05:27:27 +02:00
iceman1001 c8b51ccf25 chg: legic standalone - now saves read cards to flashmemory (RDV4)\n also simulates correct cardtype.\n It goes direct into recording / reading a tag. Once a complete dump is done, it starts to simulate 2020-03-30 15:11:48 +02:00
Uli Heilmeier db02a1f306 HF_Legic: remove global variable and cleanup
As requested by @iceman1001:
* removed global variable
* updated according to make style
* added entry in CHANGELOG.md
2020-03-30 10:22:45 +02:00
Uli Heilmeier 8c8a86cb83 Standalone mode: Adding Legic Prime read/sim run
This commit adds a standalone mode for Legic Prime.
It reads and simulates a Legic tag.
Tested with MIM1024 tags.
MIM256 and MIM512 should work to. We just read the data and for simulating
we pretend to be a MIM1024 card.

Co-authored-by: Stefanie Hofmann <>
2020-03-27 14:08:45 +01:00
Philippe Teuwen d19754567d summer restructuring:
* .h include only the strict minimum for their own parsing
  * this forces all files to include explicitment their needs and not count on far streched dependencies
  * this helps Makefile to rebuild only the minimum
  * according to this rule, most standalone .h are now gone
  * big app.h is gone
  * remove seldom __cplusplus, if c++ happens, everything will have to be done properly anyway
* all unrequired include were removed
* split common/ into common/ (client+arm) and common_arm/ (os+bootloader)
  * bring zlib to common/
  * bring stuff not really/not yet used in common back to armsrc/ or client/
  * bring liblua into client/
  * bring uart into client/
  * move some portions of code around (dbprint, protocols,...)
* rename unused files into *_disabled.[ch] to make it explicit
* rename soft Uarts between 14a, 14b and iclass, so a standalone could use several without clash
* remove PrintAndLogDevice
* move deprecated-hid-flasher from client to tools
* Makefiles
  * treat deps in armsrc/ as in client/
  * client: stop on warning (-Werror), same as for armsrc/

Tested on:

* all standalone modes
* Linux
2019-08-11 21:42:01 +02:00
iceman1001 283cc8d12a convert NG 2019-06-13 12:28:30 -04:00
Philippe Teuwen 482db05741 Rename few stuff for consistency 2019-04-18 12:49:51 +02:00
Philippe Teuwen 961d929f4d changing {} style to match majority of previous style 2019-03-10 11:20:22 +01:00
Philippe Teuwen 0373696662 make style 2019-03-10 00:00:59 +01:00
iceman1001 803aab7431 FIX: 'hf legic sim' - longer timeout for writes? (@drandreas)
see https://github.com/RfidResearchGroup/proxmark3/issues/83
2019-01-25 11:58:00 +01:00
AntiCat cd78b00815 Legic: Implemented setup phase for card simulation 2018-09-05 23:03:05 +02:00
AntiCat 61e4eac2b2 Legic: Moved card simulator into separate file & cleaned interface.
Reader and card simulation have almost no common code. Moreover the sim
uses an SSP Clock at 212kHz for all timings to prevent any drifting from
the PRNG. This clock speed is not available in reader simulation mode (SSP
runs at up to 3.4MHz, and changes speed between TX and RX). For these
reasons having the code in separate files makes it significantly cleaner.
2018-09-05 23:03:04 +02:00
Andreas Dröscher 9ba20b590a change: reduced demodulator to bare minimum
The initial code added complexity without improving reading distance.
Thankfully the peak detection signal path has a low noise floor.
2018-08-12 12:51:45 +02:00
Andreas Dröscher 0d0b651246 change: re-added trace log 2018-08-12 12:51:45 +02:00
Andreas Dröscher ff5b046903 change: re-added status LEDs
- LED_A: FPGA and 13.56MHz carrier is active
- LED_B: Reading Byte
- LED_C: Writing Byte
2018-08-12 12:41:45 +02:00
Andreas Dröscher e052fbc433 change: re-added legic write support 2018-08-12 12:41:45 +02:00
Andreas Dröscher c06f0af7f3 change: switched from timestamps (us) to ticks
GetCountUS() has a jitter of +/- 7us this is not precise
enough to keep the PRNG in sync. 1.5 * GET_TICKS on the
other hand is spot on.
2018-08-12 09:59:48 +02:00
Andreas Dröscher e0adc976e0 change: added rx/tx coordination timestamp 2018-08-12 09:59:48 +02:00
Andreas Dröscher 7244f5825d change: legic reader tx back to bigbang
I've tried to modulate the Legic specific pause-puls using ssc and the default
ssc clock of 105.4 kHz (bit periode of 9.4us) - previous commit. However,
the timing was not precise enough. By increasing the ssc clock this could
be circumvented, but the adventage over bitbang would be little.
2018-08-12 09:59:48 +02:00
Andreas Dröscher 3029223158 change: legic reader now uses xcorrelation and ssc based io
- Even tough legic tags transmit just AM using xcorrelation
   results in a significantly better signal quality.
 - Switching from bit bang to a hardware based ssc frees
   up CPU time for other tasks e.g. demodulation
2018-08-12 09:59:48 +02:00
Andreas Dröscher db70ab8f7d change: remove broken legic simulator
It will be rewritten in a later commit
2018-08-12 09:59:48 +02:00
Andreas Dröscher 8a53137ab0 change: remove dead legic code
This code was either disabled or never reached.
2018-08-12 09:59:48 +02:00
Iceman c339035ec5
Revert "WIP: Clean Legic Reader" 2018-08-06 15:05:36 +02:00
Andreas Dröscher 058426fa17 change: added rx/tx coordination timestamp 2018-08-05 00:57:20 +02:00
Andreas Dröscher 8f797d1388 change: legic reader tx back to bigbang
I've tried to modulate the Legic specific pause-puls using ssc and the default
ssc clock of 105.4 kHz (bit periode of 9.4us) - previous commit. However,
the timing was not precise enough. By increasing the ssc clock this could
be circumvented, but the adventage over bitbang would be little.
2018-08-05 00:57:20 +02:00
Andreas Dröscher 78d5188922 change: legic reader now uses xcorrelation and ssc based io
- Even tough legic tags transmit just AM using xcorrelation
   results in a significantly better signal quality.
 - Switching from bit bang to a hardware based ssc frees
   up CPU time for other tasks e.g. demodulation
2018-08-04 23:13:17 +02:00
Andreas Dröscher 1adff322b1 change: remove broken legic simulator
It will be rewritten in a later commit
2018-08-04 23:13:17 +02:00
Andreas Dröscher 33eb2f5fa0 change: remove dead legic code
This code was either disabled or never reached.
2018-08-04 23:13:17 +02:00
iceman1001 46a0ec7130 CHG: removed old TRUE/FALSE defines... some left still.. 2017-07-27 09:28:43 +02:00
iceman1001 24d332fac7 fixes.. 2017-07-11 18:27:59 +02:00
iceman1001 f8ff1483eb CHG: "hf legic sim" old imp, uses two timers, we have one. I'm seriously starting on thinking about a UART instead, to read the dmabuffer. If only I knew howto. 2016-10-10 21:52:58 +02:00
iceman1001 c2723575de CHG; added an option wither or not to clear emulator mem on init 2016-10-09 18:24:51 +02:00
iceman1001 539fd59ebe CHG: "hf legic write" - now writes on the limits better.
CHG: "hf legic restore" - now restors :)
CHG: "hf legic rdmem" - now has a nice offset row above the read data.  try:  'hf legic rdmem 0 100'
2016-10-09 15:41:31 +02:00
iceman1001 cd79d97223 CHG: syntax suger 2016-10-08 19:14:35 +02:00
iceman1001 7e7d3de5fa FIX: looks like "hf legic write" works again! 2016-10-07 23:07:59 +02:00
iceman1001 4409bf6ef3 CHG: "hf legic write" with these I managed to get one byte written. Its a start. 2016-10-07 22:16:38 +02:00
iceman1001 715bed5023 CHG: adjustments to 3.6ms 2016-10-07 21:28:09 +02:00
iceman1001 c2ab5e8c4e FIX: "hf list legic" annotation now correct prints byte and value for "legic write" command 2016-10-07 20:23:57 +02:00
iceman1001 e4d57949df FIX: wrong log bytes... 2016-10-07 19:15:08 +02:00
iceman1001 b816886806 FIX: one send command bug fixed. Turns out that uint16_t is too small for 21/23bits size. Who figured? 2016-10-07 19:11:38 +02:00
iceman1001 27c4a862f6 FIX: unused variable removed.
CHG: start remaking the used timers in "Hf legic write"
2016-10-07 12:23:07 +02:00