RfidResearchGroup/proxmark3
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102 commits

Author SHA1 Message Date
iceman1001
283cc8d12a convert NG 2019-06-13 12:28:30 -04:00
Philippe Teuwen
482db05741 Rename few stuff for consistency 2019-04-18 12:49:51 +02:00
Philippe Teuwen
961d929f4d changing {} style to match majority of previous style 2019-03-10 11:20:22 +01:00
Philippe Teuwen
0373696662 make style 2019-03-10 00:00:59 +01:00
iceman1001
803aab7431 FIX: 'hf legic sim' - longer timeout for writes? (@drandreas) 
see https://github.com/RfidResearchGroup/proxmark3/issues/83
 2019-01-25 11:58:00 +01:00
AntiCat
cd78b00815 Legic: Implemented setup phase for card simulation 2018-09-05 23:03:05 +02:00
AntiCat
61e4eac2b2 Legic: Moved card simulator into separate file & cleaned interface. 
Reader and card simulation have almost no common code. Moreover the sim
uses an SSP Clock at 212kHz for all timings to prevent any drifting from
the PRNG. This clock speed is not available in reader simulation mode (SSP
runs at up to 3.4MHz, and changes speed between TX and RX). For these
reasons having the code in separate files makes it significantly cleaner.
 2018-09-05 23:03:04 +02:00
Andreas Dröscher
9ba20b590a change: reduced demodulator to bare minimum 
The initial code added complexity without improving reading distance.
Thankfully the peak detection signal path has a low noise floor.
 2018-08-12 12:51:45 +02:00
Andreas Dröscher
0d0b651246 change: re-added trace log 2018-08-12 12:51:45 +02:00
Andreas Dröscher
ff5b046903 change: re-added status LEDs 
- LED_A: FPGA and 13.56MHz carrier is active
- LED_B: Reading Byte
- LED_C: Writing Byte
 2018-08-12 12:41:45 +02:00
Andreas Dröscher
e052fbc433 change: re-added legic write support 2018-08-12 12:41:45 +02:00
Andreas Dröscher
c06f0af7f3 change: switched from timestamps (us) to ticks 
GetCountUS() has a jitter of +/- 7us this is not precise
enough to keep the PRNG in sync. 1.5 * GET_TICKS on the
other hand is spot on.
 2018-08-12 09:59:48 +02:00
Andreas Dröscher
e0adc976e0 change: added rx/tx coordination timestamp 2018-08-12 09:59:48 +02:00
Andreas Dröscher
7244f5825d change: legic reader tx back to bigbang 
I've tried to modulate the Legic specific pause-puls using ssc and the default
ssc clock of 105.4 kHz (bit periode of 9.4us) - previous commit. However,
the timing was not precise enough. By increasing the ssc clock this could
be circumvented, but the adventage over bitbang would be little.
 2018-08-12 09:59:48 +02:00
Andreas Dröscher
3029223158 change: legic reader now uses xcorrelation and ssc based io 
- Even tough legic tags transmit just AM using xcorrelation
   results in a significantly better signal quality.
 - Switching from bit bang to a hardware based ssc frees
   up CPU time for other tasks e.g. demodulation
 2018-08-12 09:59:48 +02:00
Andreas Dröscher
db70ab8f7d change: remove broken legic simulator 
It will be rewritten in a later commit
 2018-08-12 09:59:48 +02:00
Andreas Dröscher
8a53137ab0 change: remove dead legic code 
This code was either disabled or never reached.
 2018-08-12 09:59:48 +02:00
Iceman
c339035ec5
Revert "WIP: Clean Legic Reader" 2018-08-06 15:05:36 +02:00
Andreas Dröscher
058426fa17 change: added rx/tx coordination timestamp 2018-08-05 00:57:20 +02:00
Andreas Dröscher
8f797d1388 change: legic reader tx back to bigbang 
I've tried to modulate the Legic specific pause-puls using ssc and the default
ssc clock of 105.4 kHz (bit periode of 9.4us) - previous commit. However,
the timing was not precise enough. By increasing the ssc clock this could
be circumvented, but the adventage over bitbang would be little.
 2018-08-05 00:57:20 +02:00
Andreas Dröscher
78d5188922 change: legic reader now uses xcorrelation and ssc based io 
- Even tough legic tags transmit just AM using xcorrelation
   results in a significantly better signal quality.
 - Switching from bit bang to a hardware based ssc frees
   up CPU time for other tasks e.g. demodulation
 2018-08-04 23:13:17 +02:00
Andreas Dröscher
1adff322b1 change: remove broken legic simulator 
It will be rewritten in a later commit
 2018-08-04 23:13:17 +02:00
Andreas Dröscher
33eb2f5fa0 change: remove dead legic code 
This code was either disabled or never reached.
 2018-08-04 23:13:17 +02:00
iceman1001
46a0ec7130 CHG: removed old TRUE/FALSE defines... some left still.. 2017-07-27 09:28:43 +02:00
iceman1001
24d332fac7 fixes.. 2017-07-11 18:27:59 +02:00
iceman1001
f8ff1483eb CHG: "hf legic sim" old imp, uses two timers, we have one. I'm seriously starting on thinking about a UART instead, to read the dmabuffer. If only I knew howto. 2016-10-10 21:52:58 +02:00
iceman1001
c2723575de CHG; added an option wither or not to clear emulator mem on init 2016-10-09 18:24:51 +02:00
iceman1001
539fd59ebe CHG: "hf legic write" - now writes on the limits better. 
CHG: "hf legic restore" - now restors :)
CHG: "hf legic rdmem" - now has a nice offset row above the read data.  try:  'hf legic rdmem 0 100'
 2016-10-09 15:41:31 +02:00
iceman1001
cd79d97223 CHG: syntax suger 2016-10-08 19:14:35 +02:00
iceman1001
7e7d3de5fa FIX: looks like "hf legic write" works again! 2016-10-07 23:07:59 +02:00
iceman1001
4409bf6ef3 CHG: "hf legic write" with these I managed to get one byte written. Its a start. 2016-10-07 22:16:38 +02:00
iceman1001
715bed5023 CHG: adjustments to 3.6ms 2016-10-07 21:28:09 +02:00
iceman1001
c2ab5e8c4e FIX: "hf list legic" annotation now correct prints byte and value for "legic write" command 2016-10-07 20:23:57 +02:00
iceman1001
e4d57949df FIX: wrong log bytes... 2016-10-07 19:15:08 +02:00
iceman1001
b816886806 FIX: one send command bug fixed. Turns out that uint16_t is too small for 21/23bits size. Who figured? 2016-10-07 19:11:38 +02:00
iceman1001
27c4a862f6 FIX: unused variable removed. 
CHG: start remaking the used timers in "Hf legic write"
 2016-10-07 12:23:07 +02:00
iceman1001
f0fa663814 CHG: "hf legic write" got a make over in how its called. Now called with 'offset' and 'data' 
'hf legic write o 10 d 11223344'  -  this will write 4 bytes (0x11,0x22,0x33,0x44) to tag from offset 10 (0x0A)
 2016-10-07 11:58:14 +02:00
iceman1001
e4a8d1e2ac CHG: started the process of fixing "hf legic write" and "hf legic sim" commands. 2016-10-07 00:15:47 +02:00
iceman1001
0e8cabed8d ADD: "hf legic eload" - Load binary file to emulator memory. Use "h" for help text 
ADD:  "hf legic esave" - Save emulator memory to binary file. Use "h" for help text
 2016-10-06 19:13:23 +02:00
iceman1001
9015ae0f5d CHG: "hf legic dump" now automatically detects tagtype and dumps accordingly. 
CHG:  still #define codestyle  should it be with or without semicolons?
 2016-10-05 22:58:06 +02:00
iceman1001
b1cd7d5ca6 FIX: one too many semicolons for #defines 2016-10-05 22:18:26 +02:00
iceman1001
00271f774a FIX: undeclared var on deviceside, 
FIX:  "hf legic dump" is almost there.
 2016-10-05 22:07:32 +02:00
iceman1001
633d068682 CHG: command name changes.. 
old "hf legic info" is now "hf legic reader"
old "hf legic read" is now "hf legic rdmem"
old "hf legic decode" is now "hf legic info"

ADD:  new command "hf legic dump",  which will autodetect tagtype and dump all mem to a binary file.
 2016-10-05 21:42:13 +02:00
iceman1001
635d6e9bef CHG: code clean up 2016-10-05 17:10:29 +02:00
iceman1001
c15e07f11d CHG: making timings a bit tighter == faster read of tag. Like 1ms for whole tag. 
FIX:  off-by-one bug in read-byte-loop.
 2016-10-04 23:08:39 +02:00
iceman1001
7a8db2f678 CHG: "hf legic read" - increased timeout values client side, reading MIM1024 takes a bit of time 2016-10-04 21:26:19 +02:00
iceman1001
86087eba00 Textual changes in helptext. Still no clear. 2016-10-04 18:43:11 +02:00
iceman1001
7bc3c99e7e CHG: "hf legic write" started to change this command to the updated code 2016-10-04 18:05:55 +02:00
iceman1001
77a689dbeb CHG: revert legiccrc8 to old algo. 
CHG: "hf legic decode" now loads EML memory
CHG: legic timings is better.
 2016-10-04 00:07:07 +02:00
iceman1001
0b0b182fe2 CHG: changed to use BigBuff_Eml memory instead of big_buff_malloc. 
CHG: downloading eml memory from device should use uint's
CHG: "hf legic read" has a different printing. It now prints 32bytes / row
 2016-10-03 23:24:59 +02:00